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  pci 9080 data sheet version 1.02 july 24, 1997 website: http://www.plxtech.com email: apps@plxtech.com phone: 408-774-9060 fax: 408-774-2169
pci 9080 table of contents ? plx technology, inc., 1997 page iii version 1.01 table of contents 1. general description .......................................................................................................... ....................................1 1.1 applications for the pci 9080 ............................................................................................... ........................2 1.1.1 pci adapter cards......................................................................................................... ..................................................... 2 1.1.2 embedded systems.......................................................................................................... .................................................. 2 1.2 major features.............................................................................................................. ....................................3 1.3 compatibility of pci 9080 with pci 9060, 9060es, and 9060sd................................................................4 1.3.1 pin compatibility ......................................................................................................... ........................................................ 4 1.3.2 register compatibility.................................................................................................... ..................................................... 4 1.4 comparison of pci 9060, pci 9060es, pci 9060sd, and pci 9080..............................................................5 2. bus operation................................................................................................................ ............................................6 2.1 pci bus cycles.............................................................................................................. .......................................6 2.1.1 pci target command codes.................................................................................................. ............................................ 6 2.1.2 pci master command codes .................................................................................................. ........................................... 6 2.1.2.1 dma master command codes ................................................................................................ ....................................... 6 2.1.2.2 direct local to pci command codes ....................................................................................... ...................................... 6 2.1.3 pci arbitration ........................................................................................................... ......................................................... 6 2.2 local bus cycles............................................................................................................ ...................................7 2.2.1 local bus arbitration..................................................................................................... ...................................................... 7 2.2.2 local bus direct master................................................................................................... ................................................... 7 2.2.3 local bus direct slave.................................................................................................... .................................................... 7 2.2.3.1 ready/wait state control ................................................................................................ ............................................... 7 2.2.3.1.1 wait statelocal side................................................................................................. ............................................ 7 2.2.3.1.2 wait statepci side ................................................................................................... ............................................ 8 2.2.3.2 burst mode and continuous burst mode (bterm burst terminate mode)..................................................... ................ 8 2.2.3.2.1 burst mode ............................................................................................................ ................................................... 8 2.2.3.2.2 continuous burst mode (bterm burst terminate mode).................................................................. ....................... 8 2.2.3.2.3 partial lword accesses ................................................................................................ ............................................ 9 2.2.3.3 recovery states ......................................................................................................... .................................................... 9 2.2.3.4 local bus read accesses ................................................................................................. ............................................. 9 2.2.3.5 local bus write accesses ................................................................................................ .............................................. 9 2.2.3.6 direct slave write accesses8- and 16-bit buses......................................................................... ............................... 9 2.2.3.7 local bus data parity ................................................................................................... .................................................. 9 2.2.3.8 local bus little/big endian ............................................................................................. ................................................ 9 2.2.3.8.1 32 bit local busbig endian mode ...................................................................................... ................................... 9 2.2.3.8.2 16 bit local busbig endian mode ...................................................................................... ................................. 10 2.2.3.8.3 8 bit local busbig endian mode ....................................................................................... .................................. 10
pci 9080 table of contents ? plx technology, inc., 1997 page iv version 1.01 3. functional description....................................................................................................... ................................12 3.1 reset ....................................................................................................................... .............................................12 3.1.1 pci bus input rst# ........................................................................................................ ................................................. 12 3.1.2 software reset lreseto# ................................................................................................... ........................................... 12 3.1.3 local bus input lreseti# .................................................................................................. ............................................. 12 3.1.4 local bus output lreseto# ................................................................................................. .......................................... 12 3.1.5 software reset ............................................................................................................ ..................................................... 12 3.2 pci 9080 initialization..................................................................................................... .................................12 3.2.1 serial eeprom initialization .............................................................................................. .............................................. 13 3.2.2 local initialization ...................................................................................................... ....................................................... 13 3.3 serial eeprom ............................................................................................................... ....................................13 3.3.1 short serial eeprom load.................................................................................................. ............................................ 13 3.3.2 long serial eeprom load ................................................................................................... ........................................... 14 3.3.3 extra long serial eeprom load............................................................................................. ........................................ 16 3.3.4 recommended serial eeproms ................................................................................................ ..................................... 16 3.3.5 programming the serial eeprom............................................................................................. ....................................... 16 3.4 internal register access .................................................................................................... .......................16 3.4.1 pci bus access to internal registers ...................................................................................... ......................................... 17 3.4.2 local bus access to internal registers .................................................................................... ........................................ 17 3.5 response to fifo full/empty................................................................................................. .....................18 3.6 direct data transfer modes.................................................................................................. ....................18 3.6.1 direct master operation (local master to pci target)...................................................................... ................................ 18 3.6.1.1 decode .................................................................................................................. ....................................................... 19 3.6.1.2 fifos................................................................................................................... ......................................................... 19 3.6.1.3 memory access ........................................................................................................... ................................................. 19 3.6.1.4 io/cfg access........................................................................................................... .................................................. 20 3.6.1.5 i/o ..................................................................................................................... ............................................................ 20 3.6.1.6 cfg (pci configuration type 0 or type 1 cycles)......................................................................... .............................. 20 3.6.1.7 direct bus master lock.................................................................................................. ............................................... 21 3.6.1.8 master/target abort..................................................................................................... ................................................. 21 3.6.1.9 write and invalidate .................................................................................................... .................................................. 21 3.6.1.9.1 dma write and invalidate .............................................................................................. ......................................... 21 3.6.1.9.2 direct master write and invalidate.................................................................................... ...................................... 21 3.6.2 direct slave operation (pci master to local bus access) ................................................................... ............................ 23 3.6.2.1 pci 2.1 mode............................................................................................................ .................................................... 23 3.6.2.2 pci to local address mapping ............................................................................................ ......................................... 24 3.6.2.2.1 byte enables .......................................................................................................... ................................................ 24 3.6.2.2.2 local bus initialization software ..................................................................................... ........................................ 25 3.6.2.2.3 pci initialization software........................................................................................... ............................................ 25
pci 9080 table of contents ? plx technology, inc., 1997 page v version 1.01 3.6.2.3 deadlock and breqo...................................................................................................... ............................................. 26 3.6.2.3.1 backoff............................................................................................................... ..................................................... 26 3.6.2.3.2 software/hardware solution for systems without backoff capability ..................................................... ................ 27 3.6.2.3.3 software solutions to deadlock........................................................................................ ...................................... 27 3.6.2.4 direct slave lock....................................................................................................... ................................................... 27 3.6.3 direct slave priority ..................................................................................................... ..................................................... 27 3.7 dma operation ............................................................................................................... ...................................28 3.7.1 non-chaining mode dma ..................................................................................................... ............................................ 28 3.7.2 chaining mode dma......................................................................................................... ................................................ 29 3.7.3 dma data transfers ........................................................................................................ ................................................. 31 3.7.3.1 local to pci bus dma transfer........................................................................................... ......................................... 31 3.7.3.2 pci to local bus dma transfer........................................................................................... ......................................... 32 3.7.3.3 unaligned transfers ..................................................................................................... ................................................ 32 3.7.4 demand mode dma ........................................................................................................... .............................................. 32 3.7.5 dma priority.............................................................................................................. ........................................................ 33 3.7.6 dma arbitration ........................................................................................................... ..................................................... 33 3.7.6.1 end of transfer (eot0# or eot1#) input .................................................................................. ................................... 33 3.7.6.2 dma abort ............................................................................................................... ..................................................... 33 3.7.6.3 local latency and pause timers.......................................................................................... ........................................ 33 3.8 vendor and device id registers .............................................................................................. .................34 3.9 doorbell registers .......................................................................................................... .............................34 3.10 mailbox registers.......................................................................................................... .................................34 3.11 user input and output ...................................................................................................... ............................34 3.12 interrupts ................................................................................................................. ........................................35 3.12.1 pci interrupts (inta#) ................................................................................................... ................................................... 35 3.12.1.1 local interrupt input.................................................................................................. ................................................ 35 3.12.1.2 master/target abort interrupt.......................................................................................... .......................................... 35 3.12.2 local interrupts (linto#) ................................................................................................ .................................................. 36 3.12.2.1 local to pci doorbell interrupt........................................................................................ .......................................... 36 3.12.2.2 pci to local doorbell interrupt........................................................................................ .......................................... 36 3.12.2.3 built-in self test interrupt (bist).................................................................................... .......................................... 36 3.12.2.4 dma channel 0/1 interrupts ............................................................................................. ........................................ 36 3.12.3 pci serr# (pci nmi) ...................................................................................................... ................................................ 37 3.12.4 local lserr# (local nmi)................................................................................................. .............................................. 37 3.13 i 2 0 compatible message unit ...................................................................................................... .................37 3.13.1 inbound messages ......................................................................................................... .................................................. 38 3.13.2 outbound messages........................................................................................................ ................................................. 38 3.13.3 i 2 o pointer management ........................................................................................................... ....................................... 38 3.13.4 inbound free list fifo................................................................................................... .................................................. 39
pci 9080 table of contents ? plx technology, inc., 1997 page vi version 1.01 3.13.5 inbound post list fifo ................................................................................................... .................................................. 41 3.13.6 outbound post list fifo .................................................................................................. ................................................ 41 3.13.7 outbound post queue ...................................................................................................... ................................................ 41 3.13.8 inbound free queue....................................................................................................... .................................................. 41 3.13.9 outbound free list fifo .................................................................................................. ................................................ 41 3.13.10 i 2 0 enable sequence .............................................................................................................. ...................................... 42 4. registers .................................................................................................................... ...............................................43 4.1 new register definitions summary ............................................................................................ .............43 4.1.1 register differences between pci 9080 and pci 9060, pci 9060es, and pci 9060sd............................................ ...... 44 4.2 register address mapping.................................................................................................... ......................50 4.2.1 pci configuration registers ............................................................................................... .............................................. 50 4.2.2 local configuration registers............................................................................................. .............................................. 51 4.2.3 runtime registers ......................................................................................................... ................................................... 52 4.2.4 dma registers............................................................................................................. ..................................................... 53 4.2.5 messaging queue registers................................................................................................. ............................................ 54 4.3 pci configuration registers ................................................................................................. ....................55 4.3.1 (pciidr; pci:00h, loc:00h) pci configuration id register .................................................................. .......................... 55 4.3.2 (pcicr; pci:04h, loc:04h) pci command register ............................................................................ .......................... 55 4.3.3 (pcisr; pci:06h, loc:06h) pci status register............................................................................. ................................ 56 4.3.4 (pcirev; pci:08h, loc:08h) pci revision id register ....................................................................... ........................... 56 4.3.5 (pciccr; pci:09-0bh, loc:09-0bh) pci class code register.................................................................. ..................... 57 4.3.6 (pciclsr; pci:0ch, loc:0ch) pci cache line size register .................................................................. ..................... 57 4.3.7 (pciltr; pci:0dh, loc:0dh) pci latency timer register ..................................................................... ........................ 57 4.3.8 (pcihtr; pci:0eh, loc:0eh) pci header type register ....................................................................... ........................ 57 4.3.9 (pcibistr; pci:0fh, loc:0fh) pci built-in self test (bist) register ....................................................... .................... 58 4.3.10 (pcibar0; pci:10h, loc:10h) pci base address register for memory accesses to local, runtime, and dma registers.............................................................................................................. ............................................. 58 4.3.11 (pcibar1; pci:14h, loc:14h) pci base address register for i/o accesses to local, runtime, and dma registers.................................................................................................................. ................................................ 59 4.3.12 (pcibar2; pci:18h, loc:18h) pci base address register for memory accesses to local address space 0 ............... 59 4.3.13 (pcibar3; pci:1ch, loc:1ch) pci base address register for memory accesses to local address space 1 .............. 60 4.3.14 (pcibar4; pci:20h, loc:20h) pci base address register .................................................................... ........................ 60 4.3.15 (pcibar5; pci:24h, loc:24h) pci base address register .................................................................... ........................ 60 4.3.16 (pcicis; pci:28h, loc:28h) pci cardbus cis pointer register .............................................................. ....................... 61 4.3.17 (pcisvid; pci:2ch, loc:2ch) pci subsystem vendor id register............................................................. ................... 61 4.3.18 (pcisid; pci:2eh, loc:2eh) pci subsystem id register ..................................................................... .......................... 61 4.3.19 (pcierbar; pci:30h, loc:30h) pci expansion rom base register ............................................................. ............... 61 4.3.20 (pciilr; pci:3ch, loc:3ch) pci interrupt line register ................................................................... ............................. 61 4.3.21 (pciipr; pci:3dh, loc:3dh) pci interrupt pin register .................................................................... ............................. 62 4.3.22 (pcimgr; pci:3eh, loc:3eh) pci min_gnt register .......................................................................... ........................... 62
pci 9080 table of contents ? plx technology, inc., 1997 page vii version 1.01 4.3.23 (pcimlr; pci:3fh, loc:3fh) pci max_lat register .......................................................................... ............................ 62 4.4 local configuration registers ............................................................................................... ................63 4.4.1 (las0rr; pci:00h, loc:80h) local address space 0 range register for pci to local bus ...................................... .... 63 4.4.2 (las0ba; pci:04h, loc:84h) local address space 0 local base address (remap) register ...................................... .63 4.4.3 (marbr; pci:08h or ach, loc:88h or 12ch) mode/arbitration register........................................................ ................ 64 4.4.4 (bigend; pci:0ch, loc:8ch) big/little endian descriptor register.......................................................... ..................... 65 4.4.5 (eromrr; pci:10h, loc:90h) expansion rom range register ................................................................... ................ 66 4.4.6 (eromba; pci:14h, loc:94h) expansion rom local base address (remap) register and breqo control ............... 66 4.4.7 (lbrd0; pci:18h, loc:98h) local address space 0/expansion rom bus region descriptor register......................... 67 4.4.8 (dmrr; pci:1ch, loc:9ch) local range register for direct master to pci.................................................... ............... 68 4.4.9 (dmlbam; pci:20h, loc:a0h) local bus base address register for direct master to pci memory .............................. 68 4.4.10 (dmlbai; pci:24h, loc:a4h) local base address register for direct master to pci io/cfg................................... ..... 68 4.4.11 (dmpbam; pci:28h, loc:a8h) pci base address (remap) register for direct master to pci memory ........................ 69 4.4.12 (dmcfga; pci:2ch, loc:ach) pci configuration address register for direct master to pci io/cfg.......................... 70 4.4.13 (las1rr; pci:f0h, loc:170h) local address space 1 range register for pci to local bus.................................... .... 70 4.4.14 (las1ba; pci:f4h, loc:174h) local address space 1 local base address (remap) register.................................... .71 4.4.15 (lbrd1; pci:f8h, loc:178h) local address space 1 bus region descriptor register.......................................... ........ 71 4.5 runtime registers ........................................................................................................... ...............................72 4.5.1 (mbox0; pci:40h or 78h, loc:c0h) mailbox register 0 ....................................................................... .......................... 72 4.5.2 (mbox1; pci:44h or 7ch, loc:c4h) mailbox register 1....................................................................... .......................... 72 4.5.3 (mbox2; pci:48h, loc:c8h) mailbox register 2 .............................................................................. .............................. 72 4.5.4 (mbox3; pci:4ch, loc:cch) mailbox register 3 .............................................................................. ............................. 72 4.5.5 (mbox4; pci:50h, loc:d0h) mailbox register 4 .............................................................................. .............................. 72 4.5.6 (mbox5; pci:54h, loc:d4h) mailbox register 5 .............................................................................. .............................. 73 4.5.7 (mbox6; pci:58h, loc:d8h) mailbox register 6 .............................................................................. .............................. 73 4.5.8 (mbox7; pci:5ch, loc:dch) mailbox register 7 .............................................................................. ............................. 73 4.5.9 (p2ldbell; pci:60h, loc:e0h) pci to local doorbell register ............................................................... ...................... 73 4.5.10 (l2pdbell; pci:64h, loc:e4h) local to pci doorbell register .............................................................. ....................... 73 4.5.11 (intcsr; pci:68h, loc:e8h) interrupt control/status register ............................................................. ......................... 74 4.5.12 (cntrl; pci:6ch, loc:ech) serial eeprom control, pci command codes, user i/o control, init control register .......................................................................................................... ................................................ 76 4.5.13 (pcihidr; pci:70h, loc:f0h) pci permanent configuration id register...................................................... ................. 77 4.5.14 (pcihrev; pci:74h, loc:f4h) pci permanent revision id register ........................................................... .................. 77 4.6 dma registers............................................................................................................... ....................................78 4.6.1 (dmamode0; pci:80h, loc:100h) dma channel 0 mode register ................................................................. .............. 78 4.6.2 (dmapadr0; pci:84h, loc:104h) dma channel 0 pci address register.......................................................... ........... 79 4.6.3 (dmaladr0; pci:88h, loc:108h) dma channel 0 local address register........................................................ ........... 79 4.6.4 (dmasiz0; pci:8ch, loc:10ch) dma channel 0 transfer size (bytes) register ................................................. ......... 79 4.6.5 (dmadpr0; pci:90h, loc:110h) dma channel 0 descriptor pointer register.................................................... ........... 79 4.6.6 (dmamode1; pci:94h, loc:114h) dma channel 1 mode register ................................................................. .............. 80
pci 9080 t a ble of contents ? p l x t echnolo g y , inc., 1997 page v iii versio n 1.01 4.6.7 (d m apadr1; pci:98h, loc:1 1 8h) d m a channe l 1 pci ad d ress re g is t e r .................................................................... . 81 4.6.8 (d m aladr1; pci:9ch, loc:11ch ) d m a channel 1 local ad d ress re g is t e r ....................................................... . ........ . 81 4.6.9 (d m asiz1; pci:a0h , loc:120h ) d m a channel 1 t ransfer size (byt e s) re g is t e r ................................................ . ......... . 81 4.6.10 (d m adpr1; pci:a4h, loc:12 4 h) d m a channel 1 descrip t or p o inter r eg i ste r ............................................................. . 81 4.6.11 (d m acsr0; pci:a8h, loc:12 8 h) d m a channel 0 comma n d/sta t us r e giste r .............................................................. . 82 4.6.12 (d m acsr1; pci:a9h, loc:12 9 h) d m a channel 1 comma n d/sta t us r e giste r .............................................................. . 82 4.6.13 (d m aarb; pci:ach, loc:12ch) d m a arbitratio n reg i ste r .................................................................... . ....................... . 82 4.6.14 (d m athr; pci:b0h, loc:130 h ) d m a t hresho l d re g is t e r ............................................................................................. . 83 4.7 messaging q u eu e reg i s t er s .......................................................................................................................84 4.7.1 (oplfis; pci:3 0 h, loc:b0) ou t bo u nd p o st l is t fifo in t errup t sta t us r e giste r .............................................. . ............. . 84 4.7.2 (oplfi m ; pci:34h, loc:b4) outb o und p os t l i st f i fo inter r upt m ask r e giste r ................................................ . ............ . 84 4.7.3 (iqp; pci:40h) i nb o und q u eue p ort re g is t e r ............................................................................... . .................................. . 84 4.7.4 (oqp; pci:44h) outb o und qu e ue p ort re g is t e r .............................................................................. . .............................. . 85 4.7.5 (mqcr; pci:c0h, loc:140h) m ess a gi n g que u e con f igur a t io n reg i ste r ......................................................... . ............. . 85 4.7.6 (qbar; pci:c4h, loc:14 4 h) que u e base a d dress re g is t e r ......................................................................................... . 85 4.7.7 (ifhpr; pci:c8h, loc: 1 48h) i nb o un d free h ead p oin t er re g iste r ............................................................ . .................. . 86 4.7.8 (if t pr; pci:cch, loc:14ch) i n bou n d fr e e t ail p o int e r registe r ................................................................................. . 86 4.7.9 (iphpr; pci:d0h, loc:1 5 0h) i nb o und p ost h e ad p o in t er reg i ste r ............................................................................... . 86 4.7.10 (ip t pr; pci:d4h, loc:154h ) in b oun d post t ail p o inter r egiste r ........................................................... . ....................... . 86 4.7.11 (ofhpr; pci:d8h, loc:15 8 h) out b oun d fre e head p o in t er re g is t e r ........................................................................... . 87 4.7.12 (of t pr; pci:dch, loc:15ch) outbo u nd f r ee t ail p oin t er re g is t e r ............................................................................. . 87 4.7.13 (ophpr; pci:e0h, loc:16 0 h) out b oun d pos t head p oi n ter re g is t e r ........................................................................... . 87 4.7.14 (op t pr; pci:e4h, loc:164h) ou t bou n d p o st t ail p oin t er re g iste r .......................................................... . ................... . 87 4.7.15 (qsr; pci:e8h, loc:1 6 8h) qu e ue st a t us/contr o l re g is t e r ........................................................................................... . 88 5. pin d escr i p t io n ............................................................................................................. . ..........................................89 5.1 pin su m ma r y .......................................................................................................................................................89 5.2 pin out common t o al l b u s mo d e s ............................................................................................................90 5.3 c b u s mo d e pin ou t ..........................................................................................................................................94 5.4 j bu s mode pin ou t ...........................................................................................................................................96 5.5 s bus mode pin ou t ..........................................................................................................................................98 6. elec t ri c a l specifi c a t ions................................................................................................... . ..... ......... .. ............100 7. package, signal, and pi n out specs............................................................................................................103 7.1 pa c kage mec h an i cal di m e n sio n s ............................................................................................................103 7.2 t y pi c al pci b u s mas t er a d ap t e r ............................................................................................. . ................104 7.3 9080 pin out (s, j, and c mo d es ) ..................................................................................................................105
pci 9080 table of contents ? plx technology, inc., 1997 page ix version 1.01 8. timing diagrams............................................................................................................. ...........................................106 8.1 list of timing diagrams.................................................................................................... ................................106 8.2 initialization ............................................................................................................. ............................................109 8.3 c mode ..................................................................................................................... ................................................112 8.3.1 direct slave ............................................................................................................. .............................................................. 112 8.3.2 direct master ............................................................................................................ ............................................................. 134 8.3.3 dma...................................................................................................................... ................................................................. 155 8.4 j mode..................................................................................................................... .................................................167 8.4.1 direct slave ............................................................................................................. .............................................................. 167 8.4.2 direct master ............................................................................................................ ............................................................. 174 8.4.3 dma...................................................................................................................... ................................................................. 177 8.5 s mode ..................................................................................................................... ................................................181
pci 9080 revision history ? plx technology, inc., 1997 page x version 1.01 revision history date revision comment 7/3/97 1.0 ? initial release. ? release timing diagrams. ? corrected typos and matched spec. ? changed pin 170 to nc. ? changed larbr (local/arbitration register) to marbr (mode/arbitration register). 7/10/97 1.01 ? set up hold and output timings ? change mechanical package dimension. ? complete electrical tables in section 6. ? correct timing diagrams. ? matched spec. 7/24/97 1.02 ? changed the title of section 7. ? added readyo# value to table 6-6. ? removed wr# and rd# signals from timing diagram 8-20. ? corrected titles of timing diagrams 8-20 and 8-68. ? corrected titles of sections 8.3.3 and 8.4.3.
pci 9080 pci i/o accelerator july 24, 1997 i 2 o compatible pci bus master interface chip version 1.02 for adapters and embedded systems ? plx technology, inc., 1997 page 1 version 1.02 features ? pci version 2.1 compliant bus master interface chip for adapters and embedded systems ? i 2 o compatible messaging unit ? 3.3 or 5 volt pci signaling, 5 volt core, low-power cmos in 208-pin pqfp ? two independent dma channels for local bus memory to/from pci host bus data transfers ? eight programmable fifos for zero wait state burst operation ? pci  local data transfers up to 132 mb/sec ? programmable local bus supports nonmultiplexed 32-bit address/data, multiplexed 32 or 16 bit, and slave accesses of 32, 16, or 8 bit local bus devices ? local bus runs asynchronously to the pci bus ? eight 32 bit mailbox and two 32 bit doorbell registers ? performs big endian/little endian conversion ? upward compatibility with pci 9060/9060es/9060sd 1. general description pci 9080 provides a compact, high performance pci bus master interface for adapter boards and embedded systems. the programmable local bus of the chip can be configured to directly connect a wide variety of processors, controllers and memory subsystems. pci 9080 contains an intelligent i/o (i 2 o) messaging unit that allows high performance and compatible software implementations of the i 2 o bus protocol specification. users of the pci 9060, 9060es and 9060sd chips may upgrade their products to support i 2 o, 3.3 volts and other new features with little or no change to existing hardware and software. pci 9080 provides eight programmable fifos. each operating modeslave, direct, master, and dma channelhave dedicated, independent read and write fifos. pci 9080 also allows a local processor to configure other pci devices in the system.  
  
  
    
     
             
       
 

 figure 1-1. typical adapter or block diagram
section 1 pci 9080 general description ? plx technology, inc., 1997 page 2 version 1.02         !  
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           !    " # $  !    " # %  !         !          !     " # $  !     " # %  !          ! figure 1-2. pci 9080 internal block diagram 1.1 applications for the pci 9080 1.1.1 pci adapter cards major pci adapter card applications for the pci 9080 include high performance communications, networking, disk control, multimedia, and video adapters. pci 9080 moves data between the host pci bus and adapter local bus in several ways. first, the local cpu or host processor may program the dma controller of the pci 9080 to move data between the adapter memory and host pci bus. second, pci 9080 can perform direct master transfers, whereby a local cpu or controller accesses the pci bus directly through a pci master transfer. pci 9080 also supports slave transfers in which another pci device is the master. finally, pci 9080 contains a complete messaging unit with mailbox registers, doorbell registers, and queue management pointers that can be used for message passing under the i 2 o protocol or a custom protocol. 1.1.2 embedded systems another application for pci 9080 is in embedded systems, such as network hubs and routers, printer engines, and industrial equipment. in this configuration, all four of the above-mentioned data transfer modes are used. in addition, pci 9080 supports type 0 and type 1 pci configuration cycles, which allows embedded cpu to act as the embedded system host and to configure other pci devices in the system.
section 1 pci 9080 general description ? plx technology, inc., 1997 page 3 version 1.02 1.2 major features pci 2.1 compliant. pci 9080 is compliant with all aspects of pci specification v2.1. i 2 o messaging unit. pci 9080 incorporates an i 2 o messaging unit. this enables the adapter or embedded system to communicate with other i 2 o-supported devices. i 2 o messaging unit is fully compatible with the pci extension of the i 2 o specification v1.5. dual independent programmable dma controllers with programmable fifos. pci 9080 provides two independently programmable dma controllers with programmable fifos for each channel. each channel supports nonchaining and chaining dma modes, demand mode dma, and end of transfer (eot) mode. direct bus master. pci 9080 supports memory-mapped bursts, transfer accesses, and i/o-mapped single- transfer accesses to the pci bus from the local bus master. pci 9080 also supports pci bus interlock (lock#) cycles. read and write fifos enable high- performance bursting. pci host capability. in direct master mode, pci 9080 can generate type 0 or type 1 pci configuration cycles. direct slave. pci 9080 supports burst memory mapped and single i/o-mapped accesses to the local bus. read and write fifos enable high-performance bursting. programmable local bus modes. pci 9080 is a pci bus master interface chip that connects a pci bus to one of three local bus types, selected through mode pins. pci 9080 may be connected to any local bus with a similar design with little or no glue logic. table 1-1 lists the three modes. table 1-1. programmable local bus modes mode description c 32-bit address/32-bit data, nonmultiplexed j 32-bit address/32-bit data, multiplexed s 32-bit address/16-bit data, multiplexed interrupt generator. pci 9080 can generate pci and local interrupts from several sources. clock. pci 9080 local bus interface runs from a local ttl clock and generates the necessary internal clocks. this clock runs asynchronously to the pci clock. there is a buffered pci clock (bpclko) for the local side to use. bpclko may be connected to lclk. 3.3 volt and 5 volt operation. pci 9080 core requires 5 v vcc. pci 9080 provides 3.3 or 5 volt signaling on the pci bus. the local bus operates at a 5v signaling level. serial eeprom interface. pci 9080 contains an optional serial eeprom interface that can be used to load configuration information. this is useful for loading information that is unique to a particular adapter (such as network id or vendor id). mailbox registers. pci 9080 contains eight 32 bit mailbox registers that may be accessed from the pci or local bus. doorbell registers. pci 9080 includes two 32 bit doorbell registers. one generates interrupts from the pci bus to local bus. the other generates interrupts from the local bus to the pci bus. unaligned dma transfer support. pci 9080 can transfer data on any byte boundary. big/little endian conversion. pci 9080 supports dynamic switching between big endian and little endian operations for direct slave, direct master, dma, and the internal register accesses on the local side. pci 9080 supports on-the-fly endian conversion for space 0, space 1, and expansion rom space. the local bus can be big/little endian by using the bigend# input pin or programmable internal register configuration. when bigend# is asserted, it overwrites the internal register configuration. note: pci bus is always little endian. read ahead mode. pci 9080 supports read ahead mode, where prefetched data can be read from the pci 9080 internal fifo instead of the local side. address must be subsequent to previous address and 32-bit aligned (next address = current address + 4). programmable bus wait states. pci 9080 can be programmed to keep the pci bus by generating a wait state(s), de-asserting trdy#, if write fifo becomes full. pci 9080 can also be programmed to keep the local bus. lhold is asserted, if direct slave write fifo becomes empty or direct slave read fifo becomes full. the local bus is dropped in either case when local bus latency timer is enabled and expires.
section 1 pci 9080 general description ? plx technology, inc., 1997 page 4 version 1.02 1.3 compatibility of pci 9080 with pci 9060, 9060es, and 9060sd pci 9080 is upward compatible with pci 9060, 9060es and 9060sd, except as noted in table 1-2 and section 4.1, new register definitions summary. 1.3.1 pin compatibility when upgrading from the pci 9060, 9060es or 9060sd, observe the following new pin definitions listed in table 1-2. table 1-2. pin compatibility 9060/es/sd pci 9080 pin # pin name description pin name description 170 clksel serial eeprom clock select nc C 175 ee1mc optional serial eeprom clock source eesel serial eeprom select 1=93cs46 (1k bit) 0=93cs56 (2k bit) 1.3.2 register compatibility all registers implemented in the 9060/es/sd are implemented in the pci 9080. there are a limited number of new bit definitions and several new registers. refer to section 4.1, new register definitions summary.
section 1 pci 9080 general description ? plx technology, inc., 1997 page 5 version 1.02 1.4 comparison of pci 9060, pci 9060es, pci 9060sd, and pci 9080 table 1-3. comparison of the pci 9060, pci 9060es, pci 9060sd, and pci 9080 feature pci 9060 pci 9060es pci 9060sd pci 9080 number of dma channel(s) 2 0 1 2 local address spaces 2 2 3 3 direct master mode yes yes no yes mailbox registers eight 32 bit four 32 bit four 32 bit eight 32 bit doorbell registers two 32 bit two 8 bit two 8 bit two 32 bit fifos 8 4 4 8 fifo depthdirect slave write, direct master write, dma 0 read and dma 0 write 8 lwords (32 bytes) 16 lwords (64 bytes) 16 lwords (64 bytes) 32 lwords (128 bytes) fifo depth direct slave read, direct master read, dma 1 read and dma 1 write 8 lwords (32 bytes) 16 lwords (64 bytes) 16 lwords (64 bytes) 16 lwords (64 bytes) llocko# pin for lock cycles no yes yes yes waiti# pin for wait state generation no yes yes yes bpclko pin; buffered pci clock no yes yes yes dreq# and dack# pins for demand mode dma support yes no yes (channel 1 only) yes register addresses identical except 9060es has no dma registers and tables 25, 26, and 43 were added identical, except 9060sd has one dma register and tables 4-29 and 4-30 were added identical except pci 9080 has additional i 2 o related registers and 30h, 34h, 40h, and 44h were remapped pin out note: pci 9080 includes all changes made for pci 9060, pci 9060es, and pci 9060sd. signals deleted: dreq0# (pin 29) dack0# (pin 30) input signals added: waiti# (pin 6) bigend# (pin 48) output signals added: bpclko (pin 168) llocko# (pin 7) signals deleted: breq (pin 21) dmpaf# (pin 8) dreq0# (pin 29) dack0# (pin 30) btermo# (pin 28) input signals added: waiti# (pin 6) bigend# (pin 48) eot0# (pin 164 in c mode, pin 5 in j and s modes) output signals added: bpclko (pin 168) llocko# (pin 7) input signal added: eot1# (pin 163) signal changed: eesel (pin 175) big/little endian conversion no yes yes yes spec. 2.1 deferred reads no yes yes yes programmable prefetch counter no yes yes yes write and invalidate cycle no yes yes yes additional device and vendor id register no yes yes yes i 2 o messaging unit no no no yes 3.3 v pci bus signaling no no no yes
section 2 pci 9080 bus operation ? plx technology, inc., 1997 page 6 version 1.02 2. bus operation 2.1 pci bus cycles pci 9080 is compliant with pci specification v2.1. refer to the pci 2.1 spec for any specific features of the pci bus. 2.1.1 pci target command codes as a target, pci 9080 allows access to pci 9080 internal registers and local bus, using the commands listed in table 2-1. table 2-1. pci target command codes command type code (c/be[3:0]#) i/o read 0010 (2h) i/o write 0011 (3h) memory read 0110 (6h) memory write 0111 (7h) memory read multiple 1100 (ch) memory read line 1110 (eh) memory write and invalidate 1111 (fh) configuration read 1010 (ah) configuration write 1011 (bh) all read or write accesses to pci 9080 can be byte, word, or longword (lword) accesses. all memory commands are aliased to the basic memory commands. all i/o accesses to pci 9080 are decoded to an lword boundary. the byte enables are used to determine which bytes are read or written. an i/o access with illegal byte enable combinations is terminated with a target abort. 2.1.2 pci master command codes pci 9080 can access the pci bus to perform dma transfers or direct master local to pci bus transfers. during the direct master or dma transfer, the command code assigned to pci 9080 internal register location (pci:6ch)(loc:ech) bits [15:0] is used as the pci command code (refer to table 4-59[15:0]). table 2-2 through table 2-5 list the various pci master command codes. note: programmable internal registers determine pci command codes when the pci 9080 is master. note: dma cannot perform i/o or configuration accesses. 2.1.2.1 dma master command codes dma controllers of pci 9080 can generate the memory cycles listed in table 2-2. table 2-2. dma master command codes command type code (c/be[3:0]#) memory read 0110 (6h) memory write 0111 (7h) memory read multiple 1100 (ch) memory read line 1110 (eh) memory write and invalidate 1111 (fh) 2.1.2.2 direct local to pci command codes for direct local to pci bus accesses, pci 9080 generates the cycles listed in table 2-3 through table 2-5. table 2-3. local to pci memory access command type code (c/be[3:0]#) memory read 0110 (6h) memory write 0111 (7h) memory read multiple 1100 (ch) memory read line 1110 (eh) table 2-4. local to pci i/o access command type code (c/be[3:0]#) i/o read 0010 (2h) i/o write 0011 (3h) table 2-5. local to pci configuration access command type code (c/be[3:0]#) configuration memory read 1010 (ah) configuration memory write 1011 (bh) 2.1.3 pci arbitration pci 9080 asserts output req# to request the pci bus. pci 9080 can be programmed using bit 23 of (pci:08h or pci:ach)(loc:88h or loc:12ch) (refer to table 4- 35[23]) to de-assert req# when it asserts frame# during a bus master cycle, or to keep req# asserted for the entire bus master cycle. pci 9080 always de-asserts
section 2 pci 9080 bus operation ? plx technology, inc., 1997 page 7 version 1.02 req# for a minimum of two pci clocks between bus master ownership that includes a target disconnect. the direct master write delay bits (bits [15:14]) of the dmpbam register (pci:28h)(loc:a8h) can be programmed to delay the pci 9080s assertion of the pci req# signal during a direct master write cycle. this register can be programmed to wait 0, 4, 8, or 16 pci bus clocks after the pci 9080 has received its first write data from the local master and is ready to begin the pci write transaction. this feature is useful in applications where the local master is bursting and the local bus clock is slower than the pci bus clock. this allows write data to accumulate in the pci 9080s direct master write fifo, which provides for better pci bus utilization. 2.2 local bus cycles pci 9080 connects a pci host bus to several local processor bus types, as listed in table 2-6. it operates in one of three modes, selected through mode pins 9 and 10, corresponding to three bus typesc, j, and s. table 2-6. local processor bus types bit 9 bit 10 mode bus type 0 0 c 32-bit nonmultiplexed 0 1 j 32-bit multiplexed 1 0 s 16-bit multiplexed 11reserved 2.2.1 local bus arbitration when pci 9080 owns the local bus, both its lhold output and lholda input are asserted. when pci 9080 samples breq asserted during a dma transfer or direct slave write transfer, it gives up the local bus within two lword transfers by de-asserting lhold and floating its local bus outputs if breq is gated or disabled, or if gating is enabled and the local bus latency timer expires. the local arbiter can now grant the local bus to another local master. after pci 9080 samples that its lholda is de-asserted and its local pause timer is zero, it re-asserts lhold to request the local bus. when the pci 9080 receives lholda, it drives the bus and continues from where it left off. 2.2.2 local bus direct master local bus cycles can be continuous single or burst cycles (programmable by way of the pci 9080 internal registers). as a local bus target, pci 9080 allows access to pci 9080 internal registers and pci bus. in c and j modes, local bus direct master accesses to the pci 9080 must be for a 32 bit nonpipelined bus. in s mode, local bus direct master accesses to the pci 9080 must be for a 16 bit nonpipelined bus. 2.2.3 local bus direct slave pci bus master read/write to local bus (pci 9080 is a pci bus target and local bus master). 2.2.3.1 ready/wait state control   
 

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 /  ) figure 2-1. wait states if readyi# input is disabled, external readyi# input has no effect on wait states for a local access. wait states between data cycles are generated internally by a wait state counter. wait state counter is initialized with its configuration register value at the start of each data access. if readyi# is enabled, readyi# has no effect until the wait state counter is 0. readyi# then controls the number of additional wait states. bterm# input is not sampled until the wait state counter is 0. bterm# overrides readyi# when bterm# is asserted. 2.2.3.1.1 wait statelocal side with direct master mode and accessing pci 9080 registers (pci 9080 local as slave): ? pci 9080 generates wait states with readyo# ? local processor generates wait states with waiti#
section 2 pci 9080 bus operation ? plx technology, inc., 1997 page 8 version 1.02 with direct slave and dma modes (pci 9080 local as master): ? pci 9080 generates wait states with waito# ? local processor generates wait states with readyi# ? use table 4-39[21:18, 5:2], table 4-62[5:2], and table 4-67[5:2] to program the number of wait states 2.2.3.1.2 wait statepci side when the wait state occurs on the pci side, master throttles irdy# and slave throttles trdy#. 2.2.3.2 burst mode and continuous burst mode (bterm burst terminate mode) table 2-7. burst and bterm on the local side mode burst bterm result single cycle 0 0 one ads# per data (default) single cycle 0 1 still one ads# per data burst-4 1 0 one ads# per four data (use this mode for i960) burst forever 1 1 one ads# per bterm# on the local side, blast# and bterm# perform the following: ? if burst is enabled (table 4-39[26,24] for non-dma, table 4-62[8] and table 4-67[8] for dma), but bterm is disabled (table 4-39[7], table 4-62[7] and table 4-67[7]), then pci 9080 bursts four lwords. blast# is generated at the fourth lword (la[3:2]=11), new ads# at the first lword (la[3:2]=00) of the next burst. ? if bterm# sampling is enabled and bterm# is low, pci 9080 forces a new ads#, but does not generate a new blast#. ? bterm# input is only valid when the pci 9080 is the master of the local bus (direct slave or dma modes). ? bterm# is generated by external logic. it is input to the pci 9080 (and i960) and used to tell the pci 9080 (and i960) to break up a burst cycle. ? bterm# is used for example to signal memory access is crossing the page boundary. on the pci side, burst is always enabled. note: if bterm is disabled, the pci 9080 performs the following: ? 32 bit local busburst up to four lwords ? 16 bit local busburst up to two lwords ? 8 bit local busburst up to one lword in every case, it performs four transactions. note: in the following sections, bterm refers to pci 9080 internal register bit. bterm# refers to the pci 9080 external signal. 2.2.3.2.1 burst mode if bursting is enabled and bterm# input is not enabled, bursting can start on any boundary and continue up to an address boundary, as described in table 2-8. after the data at the boundary is transferred, pci 9080 generates a new address cycle (ads#). table 2-8. burst mode bus mode burst c, j 32-bit busfour lwords or up to a quad lword boundary (la3, la2 = 11) c, j 16-bit busfour words or up to a quad word boundary (la2, la1 = 11) c, j 8-bit busfour bytes or up to a quad byte boundary (la1, la0 = 11) s 16-bit buseight words or up to a quad lword boundary (la3, la2 = 11) 2.2.3.2.2 continuous burst mode (bterm burst terminate mode) bterm mode enables pci 9080 to perform long bursts to devices that can accept longer than four lword bursts. pci 9080 generates one address cycle and continues to burst data. if a device requires a new address cycle after a certain address boundary, it can assert bterm# input to cause the pci 9080 to generate a new address cycle. bterm# input acknowledges the current data transfer and requests that a new address cycle be generated (ads#). the address will be for the next data transfer. if bterm mode is enabled, pci 9080 asserts blast# only if its fifos become full/empty or if a transfer is complete. note: if bterm# is asserted, blast# does not assert until the previously described conditions are met.
section 2 pci 9080 bus operation ? plx technology, inc., 1997 page 9 version 1.02 2.2.3.2.3 partial lword accesses lword accesses in which not all byte enables are asserted are broken into single address and data cycles, as listed in table 2-9. table 2-9. partial lword accesses register value (pci:18h)(loc:98h) burst enable bterm enable result (number of transfers) 0 0 single cycle (default) 0 1 single cycle 1 0 burst four lwords at a time 1 1 continuous burst mode 2.2.3.3 recovery states in j and s modes, pci 9080 inserts one recovery state between the last data transfer and next address cycle. pci 9080 does not support the 80960j feature of using readyi# input to add recovery states. no additional recovery states are added if readyi# input remains asserted during the last data cycle. 2.2.3.4 local bus read accesses for all single cycle local bus read accesses, pci 9080 reads only bytes corresponding to byte enables requested by the pci initiator. for all burst cycle single cycle bus read accesses, pci 9080 reads only lwords. 2.2.3.5 local bus write accesses for local bus writes, only the bytes specified by a pci bus master or pci 9080 dma controller are written. access to an 8- or 16-bit bus results in the pci bus lword being broken into multiple local bus transfers. for each transfer, the byte enables are encoded as in the 80960c to provide local address bits la[1:0]. 2.2.3.6 direct slave write accesses8- and 16-bit buses a direct pci access to an 8- or 16-bit bus results in the pci bus lword being broken into multiple local bus transfers. for each transfer, the byte enables are encoded as in the 80960c to provide local address bits la[1:0]. 2.2.3.7 local bus data parity there is one data parity pin for each byte lane of the pci 9080 data bus (dp[3:0]). even data parity is generated for each lane during local bus reads from pci 9080 and during pci 9080 master writes to the local bus. even data parity is checked during local bus writes to pci 9080 and during pci 9080 reads from the local bus. parity is checked for each byte lane with an asserted byte enable. pchk# is asserted in the clock cycle following the data being checked if a parity error is detected. generation or use of local bus data parity is optional. the signals on data parity pins do not effect operation of pci 9080. pci bus parity checking and generation is independent of local bus parity checking and generation. 2.2.3.8 local bus little/big endian pci bus is a little endian bus (that is, data is lword aligned to the lowermost byte lane). byte 0 (address 0) appears in ad[7:0], byte 1 appears in ad[15:8], byte 2 appears in ad[23:16] and byte 3 appears in ad[31:24]. pci 9080 local bus can be programmed to operate in big or little endian mode, as listed in table 2-10. table 2-10. big / little endian program mode bigend# pin register 1=big, 0=little endian 00big 01big 1 0 little 11big for configuration cycles, refer to table 4-36[0]. for direct master, memory, and i/o cycles, refer to table 4- 36[1]. for direct slave cycles, refer to table 4-36[2], space 0, and table 4-36[3], expansion rom. in big endian mode, pci 9080 transposes the data byte lanes. data is transferred as listed in table 2-11 through table 2-15. 2.2.3.8.1 32 bit local busbig endian mode data is lword aligned to the uppermost byte lane. byte lanes and burst orders are listed in table 2-11 and illustrated in figure 2-2.
section 2 pci 9080 bus operation ? plx technology, inc., 1997 page 10 version 1.02 table 2-11. upper lword lane transfer burst order byte lane byte 0 appears on local data [31:24] byte 1 appears on local data [23:16] byte 2 appears on local data [15:8] first transfer byte 3 appears on local data [7:0]   
   
                     figure 2-2. big/little endian32 bit local bus 2.2.3.8.2 16 bit local busbig endian mode for a 16 bit local bus, pci 9080 can be programmed to use the upper or lower word lane. byte lanes and burst order are listed in table 2-12 and table 2-13 and illustrated in figure 2-3. table 2-12. upper word lane transfer burst order byte lane byte 0 appears on local data [31:24] first transfer byte 1 appears on local data [23:16] byte 2 appears on local data [31:24] second transfer byte 3 appears on local data [23:16] table 2-13. lower word lane transfer burst order byte lane byte 0 appears on local data [15:8] first transfer byte 1 appears on local data [7:0] byte 2 appears on local data [15:8] second transfer byte 3 appears on local data [7:0]   
   
   
                    
 
    
   
       
   
   figure 2-3. big/little endian16 bit local bus 2.2.3.8.3 8 bit local busbig endian mode for an 8 bit local bus, pci 9080 can be programmed to use the upper or lower byte lane. byte lanes and burst order are listed in table 2-14 and table 2-15 and illustrated in figure 2-4. table 2-14. upper byte lane transfer burst order byte lane first transfer byte 0 appears on local data [31:24] second transfer byte 1 appears on local data [31:24] third transfer byte 2 appears on local data [31:24] fourth transfer byte 3 appears on local data [31:24] table 2-15. lower byte lane transfer burst order byte lane first transfer byte 0 appears on local data [7:0] second transfer byte 1 appears on local data [7:0] third transfer byte 2 appears on local data [7:0] fourth transfer byte 3 appears on local data [7:0]
section 2 pci 9080 bus operation ? plx technology, inc., 1997 page 11 version 1.02   
   
                    
 
 
  
                
   
   figure 2-4. big/little endian8 bit local bus for each of the following transfer types, pci 9080 local bus can be independently programmed to operate in little endian or big endian mode: ? local bus accesses to pci 9080 configuration registers ? direct slave pci accesses to local address space 0 ? direct slave pci accesses to local address space 1 ? direct slave pci accesses to expansion rom ? dma channel 0 accesses to the local bus ? dma channel 1 accesses to the local bus ? direct master accesses to pci bus for local bus configuration accesses, an input pin can be used to dynamically change the endian mode. notes: pci bus is always little endian mode. only byte lanes are swapped, not individual bits.
section 3 pci 9080 functional description ? plx technology, inc., 1997 page 12 version 1.02 3. functional description functional operation described can be changed or modified, depending on the register configuration. 3.1 reset 3.1.1 pci bus input rst# pci bus rst# input pin is a pci host reset. it causes all pci bus outputs to float, resets the entire pci 9080 and causes the local reset output, lreseto#, to be asserted. if you have a pci host, table 4-11[2:0] (master enable, memory space, i/o space) is programmed by the host after initialization is complete (table 4- 59[31]=1). (refer to figure 3-1.)   
       

 
    

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   figure 3-1. reset and initialization process 3.1.2 software reset lreseto# when asserted, the lreseto# software reset bit (table 4-59[30]) resets pci 9080 local configuration and local dma registers. however, it does not reset the pci configuration and shared runtime registers. when the bit is set, pci 9080 responds to pci accesses, but not to local accesses. pci 9080 remains in this condition until pci host clears the bit. the serial eeprom is reloaded if table 4-59[29] is set. 3.1.3 local bus input lreseti# when asserted, the lreseti# input resets the local bus portion of pci 9080, clears all local configuration and dma registers and causes lreseto# output to be asserted. 3.1.4 local bus output lreseto# lreseto# is asserted when pci bus rst# input is asserted, the lreseti# input is asserted, or the software reset bit in the init control register is set to 1. 3.1.5 software reset a host on the pci bus can set the software reset bit in the init control register to reset pci 9080 and assert the lreseto# output. all local configuration and dma registers reset. pci configuration registers do not reset. when the software reset bit is set, pci 9080 responds to pci accesses, but not to local bus accesses. pci 9080 remains in this reset condition until the pci host clears the bit. note: the local side cannot clear this reset bit because the local bus is in a reset state. 3.2 pci 9080 initialization pci 9080 configuration registers can be programmed by an optional serial eeprom and/or by a local processor, as listed in table 3-1. the serial eeprom can be reloaded by setting bit 29 of (loc:ech), serial eeprom control register (refer to table 4-59[29]). in general, pci 9080 retries all pci cycles until the local init done bit is set or nb# is low. note: internal configuration register can also be accessed by the pci host processor after power-on.
section 3 pci 9080 functional description ? plx technology, inc., 1997 page 13 version 1.02 table 3-1. nb# and serial eeprom guidelines nb# serial eeprom system boot condition no boot with pci 9080 default values. programmed boot with serial eeprom values. low blank not recommended (uses default values). no local processor programs pci 9080 registers, then sets local init status (table 4-59[31] = done). note: some systems hang if direct slave reads and writes take too long (during initialization, the pci host also performs direct slave accesses). value of pci target retry delay clocks (table 4-39[31:28]) may resolve this problem. programmed load serial eeprom, but local processor can reprogram pci 9080. high blank load serial eeprom (default values), but local processor can reprogram pci 9080. system can boot. note: serial eeprom can be programmed through pci 9080 after system boots in this condition. 3.2.1 serial eeprom initialization during serial eeprom initialization, pci 9080 response to pci target accesses is retry. during serial eeprom initialization, pci 9080 response to a local processor is to hold off readyo#. 3.2.2 local initialization pci 9080 issues a retry to all pci accesses until the "local init done bit" in the init control register is set. "init done bit" is programmable through local bus configuration accesses. if this bit is not going to be set by a local processor, then nb# input should be tied low. holding nb# input low externally forces the local init done bit to 1. pci 9080 default values are used if a serial eeprom is not present and local init status bit is set to 1 by holding the nb# input low or set by the local processor. 3.3 serial eeprom after reset, pci 9080 attempts to read the serial eeprom to determine its presence. an active low start bit indicates the serial eeprom is present (pci 9080 supports 93cs46 (1k) or 93cs56 (2k), selectable by way of the eesel pin). (refer to the manufacturers data sheet for the particular serial eeprom being used.) the first word is then checked to verify the serial eeprom is programmed. if the first word (16 bit) is all ones, a blank serial eeprom pci 9080 uses default values instead. the 5 v serial eeprom clock (eesk, pin 173) is derived from the pci clock. pci 9080 generates the serial eeprom clock by internally dividing the pci clock by 32. the serial eeprom can be read or programmed from the pci or local bus. bits [27:24] of the serial eeprom control register (refer to table 4-59[27:24]) controls the pci 9080 pins that enable the reading or writing of serial eeprom data bits. (refer to the manufacturers data sheet for the particular serial eeprom being used.) pci 9080 has three serial eeprom load options: ? short load mode short# input pin is pulled down and pci 9080 loads five lwords from the serial eeprom ? long load mode short# input pin is pulled up, bit 25 of the local bus region descriptor register (loc:98h) is set to 0, and pci 9080 loads 17 lwords from the serial eeprom (refer to table 4-39) ? extra long load mode short# input pin is pulled up, bit 25 of the local bus region descriptor register (loc:98h) is set to 1 during long load from the serial eeprom, and pci 9080 loads 21 lwords from the serial eeprom (refer to table 4-39) 3.3.1 short serial eeprom load the registers listed in table 3-2 are loaded from serial eeprom after reset is de-asserted if short# pin is low. the serial eeprom is organized in words (16 bit). pci 9080 first loads msw (most significant word; bits [31:16]), starting from the most significant bit (bit 31). pci 9080 then loads lsw (least significant word; bits [15:0]), starting again from the most significant bit (bit 15). therefore, pci 9080 loads device id, vendor id, class code, and so forth. the five 32-bit words are stored sequentially in the serial eeprom.
section 3 pci 9080 functional description ? plx technology, inc., 1997 page 14 version 1.02 table 3-2. short serial eeprom load registers serial eeprom offset description sample serial eeprom value 0 device id 9080 2 vendor id 10b5 4 class code 0680 6 class code, revision 0002 8 maximum latency, minimum grant 0000 a interrupt pin, interrupt line routing 0100 c msw of mailbox 0 (user defined) xxxx e lsw of mailbox 0 (user defined) xxxx 10 msw of mailbox 1 (user defined) xxxx 12 lsw of mailbox 1 (user defined) xxxx 3.3.2 long serial eeprom load the registers listed in table 4-39 are loaded from serial eeprom after reset is de-asserted if short# pin is high. the serial eeprom is organized in words (16 bit). pci 9080 first loads msw (most significant word; bits [31:16]), starting from the most significant bit (bit 31). pci 9080 then loads lsw (least significant word; bits [15:0]), starting again from the most significant bit (bit 15). therefore, pci 9080 will load device id, vendor id, class code, and so forth. the serial eeprom value can be entered into a data i/o programmer in the order shown below. the values shown are examples and must be modified for each particular application. the 34 16-bit words listed in the table are stored sequentially in the serial eeprom.
section 3 pci 9080 functional description ? plx technology, inc., 1997 page 15 version 1.02 table 3-3. long serial eeprom load registers serial eeprom offset description 0 device id 2 vendor id 4 class code 6 class code, revision 8 maximum latency, minimum grant a interrupt pin, interrupt line routing c msw of mailbox 0 (user defined) e lsw of mailbox 0 (user defined) 10 msw of mailbox 1 (user defined) 12 lsw of mailbox 1 (user defined) 14 msw of range for pci to local address space 0 16 lsw of range for pci to local address space 0 18 msw of local base address (remap) for pci to local address space 0 1a lsw of local base address (remap) for pci to local address space 0 1c msw of local arbitration register 1e lsw of local arbitration register 20 msw of local bus big/little endian descriptor register 22 lsw of local bus big/little endian descriptor register 24 msw of range for pci to local expansion rom 26 lsw of range for pci to local expansion rom 28 msw of local base address (remap) for pci to local expansion rom 2a lsw of local base address (remap) for pci to local expansion rom 2c msw of bus region descriptors for pci to local accesses 2e lsw of bus region descriptors for pci to local accesses 30 msw of range for direct master to pci 32 lsw of range for direct master to pci 34 msw of local base address for direct master to pci memory 36 lsw of local base address for direct master to pci memory 38 msw of local bus address for direct master to pci io/cfg 3a lsw of local bus address for direct master to pci io/cfg 3c msw of pci base address (remap) for direct master to pci 3e lsw of pci base address (remap) for direct master to pci 40 msw of pci configuration address register for direct master to pci io/cfg 42 lsw of pci configuration address register for direct master to pci io/cfg
section 3 pci 9080 functional description ? plx technology, inc., 1997 page 16 version 1.02 3.3.3 extra long serial eeprom load an extra long load mode is provided in the pci 9080 (refer to table 4-39) to load an additional five lwords from the serial eeprom. if bit 25 is set to 1 in the local bus region descriptor register (loc:98h) (refer to table 4-39), the following five lword registers are loaded in addition to normal long load process (refer to section 3.3.2, long serial eeprom load). bit 25 must be set to 1 during the long load process. (refer to table 3-4.) table 3-4. extra long serial eeprom load registers serial eeprom offset description 44 subsystem id 46 subsystem vendor id 48 msw of range for pci to local address space 1 (1 mb) 4a lsw of range for pci to local address space 1 (1 mb) 4c msw of local base address (remap) for pci to local address space 1 4e lsw of local base address (remap) for pci to local address space 1 50 msw of bus region descriptors (space 1) for pci to local accesses 52 lsw of bus region descriptors (space 1) for pci to local accesses 54 msw of pci base address for local expansion rom 56 lsw of pci base address for local expansion rom 3.3.4 recommended serial eeproms a 1k bit (national nm93cs46 or compatible) or 2k bit (national nm93cs56 or compatible) device can be used. table 3-5 lists the recommended serial eeprom loads. refer also to table 5-2 in section 5, pin description. table 3-5. recommended serial eeprom loads load unused bytes for cs46 (1k) unused bytes for cs56 (2k) short 108 364 long 60 316 extra long 40 296 note: pci 9080 does not support serial eeproms that do not support sequential read and write (such as the nm93c46 or nm93c56). 3.3.5 programming the serial eeprom the serial eeprom can be written or read, using bits [28:24] of the serial eeprom control register (refer to table 4-59[28:24]). 3.4 internal register access pci 9080 chip provides several internal registers, allowing for maximum flexibility in bus interface design and performance. the register types are accessible from both the pci and local buses, including the following: ? pci configuration registers ? local configuration registers ? mailbox registers ? doorbell registers ? dma registers ? messaging queue registers (i 2 o) figure 3-2 illustrates how these registers are accessed.     
  
 

 
   

 
   
    
 
       
      
 
    
     
  
 figure 3-2. pci 9080 internal register access
section 3 pci 9080 functional description ? plx technology, inc., 1997 page 17 version 1.02 3.4.1 pci bus access to internal registers pci 9080 pci configuration registers can be accessed from the pci bus with a configuration type 0 cycle. pci 9080 internal registers can be accessed by a memory cycle, with the pci bus address that matches the base address specified in the pci base address 0 for memory mapped configuration register of pci 9080. they can also be accessed by an i/o cycle, with the pci bus address matching the base address specified in the pci base address 1 for i/o mapped configuration register of the pci 9080. all pci read or write accesses to the pci 9080 registers can be byte, word, or lword accesses. all pci memory accesses to the pci 9080 registers can be burst or non- burst. pci 9080 responds with a pci disconnect for all burst i/o accesses to pci 9080 registers. 3.4.2 local bus access to internal registers the local processor can access all the internal registers of the pci 9080 through either internal or external address decode logic. pci 9080 provides an address decode mode pin (admode) that selects whether the internal address decode logic is used or whether the designer will supply an external chip select from an external address decoder. figure 3-3 illustrates how the dual address decode logic works. if the address decode mode pin is set to 1, internal pci 9080 address decode logic is enabled. in this mode, pci 9080 internal registers are selected when local address bits la[31:29] match input address select pins s[2:0]. if the address decode mode pin is set to 0, pci 9080 responds to local bus access when s0 is asserted low through external chip select logic. notes: s0 must be decoded while ads# is low. if admode is 1 la[31:29], specify 512 mb of local memory space allocated for accessing internal registers. all local read or write accesses to the pci 9080 registers can be byte, word, or lword accesses. all local accesses to the pci 9080 registers can be burst or non- burst. for c and j modes, accesses must be for a 32 bit nonpipelined bus. pci 9080 readyo# indicates a data transfer is complete. for s mode, accesses must be for a 16 bit nonpipelined bus. pci 9080 readyo# indicates a data transfer is complete.         
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  figure 3-3. dual address decode mode
section 3 pci 9080 functional description ? plx technology, inc., 1997 page 18 version 1.02 3.5 response to fifo full/empty table 3-6 lists the response of the pci 9080 to full and empty fifos. table 3-6. response to fifo full/empty mode direction fifo pci side local side full no action de-assert readyo# direct master write local to pci empty de-assert req# (off pci bus) no action full de-assert req# or throttle irdy# no action direct master read pci to local empty no action de-assert readyo# full disconnect or throttle trdy# no action direct slave write pci to local empty no action de-assert lhold, assert blast# (see note) full no action de-assert lhold, assert blast# (see note) direct slave read local to pci empty throttle trdy# no action full no action de-assert lhold, assert blast# local to pci empty de-assert req# no action full de-assert req# no action dma pci to local empty no action de-assert lhold, assert blast# note: de-assert of lhold depends on marbr[21]. 3.6 direct data transfer modes figure 3-4 and figure 3-5 illustrate the direct data transfer modes. refer also to table 3-6 for responses to full and empty fifos.   


   
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 figure 3-5. mailbox/doorbell message passing 3.6.1 direct master operation (local master to pci target) pci 9080 supports the direct access of the pci bus by the local processor or an intelligent controller. master mode must be enabled in the pci command register. five registers are used to define local to pci access: ? range ? local base address for direct master to pci memory register ? local base address for direct master to pci io/cfg register
section 3 pci 9080 functional description ? plx technology, inc., 1997 page 19 version 1.02 ? pci configuration address register for direct master to pci io/cfg ? pci base address 3.6.1.1 decode the range register specifies the local address bits to use for decoding a local to pci access. the local processor can perform only memory cycles. therefore, the local base address for direct master to pci memory register is used to decode an access to pci memory space and the local base address for direct master to pci io/cfg register is used to decode an access to pci i/o space or pci bus configuration cycle access. 3.6.1.2 fifos for direct master memory access to the pci bus, pci 9080 has a 32 lword (128 byte) write fifo and a 16 lword (64 byte) read fifo. fifos enable the local bus to operate independently of the pci bus and allows high- performance bursting on local and pci buses. in a direct master write, the local processor (master) writes data to pci (slave). in a direct master read, the local processor (master) reads data from pci (slave). figure 3-6 and figure 3-7 illustrate the fifos during a direct master write and read.   
 
 
 
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 figure 3-7. direct master read 3.6.1.3 memory access the local processor can read or write to the pci memory. pci 9080 converts the local read/write access. the local address space starts from the direct master local base address up to the range. remap (pci base address) defines the pci starting address. writes pci 9080 continues to accept writes and return readyo# until write fifo is full. it then holds off readyo# until space becomes available in the write fifo. a programmable direct master fifo almost full status output is provided (dmpaf#). reads pci 9080 holds off readyo# while gathering an lword from the pci bus. programmable prefetch modes are available if prefetch is enabled: prefetch, 4, 8, 16, or continuous until direct master cycle ends. the read cycle is terminated when the local blast# input is asserted. unused read data is flushed from the fifo. pci 9080 does not prefetch read data for single cycle direct master reads (local blast# input asserted during first data phase). in this case, pci 9080 reads a single pci lword. for direct master single cycle reads, pci 9080 asserts the same pci bus byte enables as asserted on the local bus. for multiple cycle reads, pci 9080 reads entire lwords (all pci byte enables are asserted), regardless of local byte enables. if the prefetch limit bit dmpbam (pci:28h)(loc:a8h) (refer to table 4-43[11]) is enabled, pci 9080 does not prefetch past a 4k boundary. also, the local side must not cross a 4k boundary during a burst read.
section 3 pci 9080 functional description ? plx technology, inc., 1997 page 20 version 1.02 pci 9080 never prefetches beyond the region specified for direct master accesses. 3.6.1.4 io/cfg access when a local direct master i/o access to the pci bus is made, the pci configuration address registers configuration enable bit determines if an i/o or configuration access is to be made to the pci bus. local burst accesses are broken into single pci i/o address/data cycles. pci 9080 does not prefetch read data for i/o and cfg reads. for direct master i/o or configuration cycles, pci 9080 asserts the same pci bus byte enables as asserted on the local bus. 3.6.1.5 i/o if the configuration enable bit is clear, a single i/o access is made to the pci bus. the local address, remapped decode address bits and the local byte enables are encoded to provide the address and is output with an i/o read or write command during the pci address cycle. for writes, data is loaded into the write fifo and readyo# returned to the local bus. for reads, pci 9080 holds off readyo# while gathering an lword from the pci bus. when the i/o remap select bit is set to a value of 1, these pci address bits [31:16] are forced to a value of 0 (refer to table 4-43[13]). 3.6.1.6 cfg (pci configuration type 0 or type 1 cycles) if the configuration enable bit is set, a cfg access is made to the pci bus. in addition to enabling the configuration (bit 31) of (pci:2ch)(loc:ach) (refer to table 4-44[31]), the user must provide all register information. the register number (bits [7:2]) or the device number (bits [15:11]) must be modified and a new cft read/write cycle must be performed before other registers or devices can be accessed. if the pci configuration address register selects a type 0 command, bits [10:0] from the register are copied to address bits [10:0]. bits [15:11] (device number) are translated into a single bit being set in pci address bits [31:11]. pci address bits [31:11] can be used as a device select. for a type 1 command, bits [23:0] are copied from the register to bits [23:0] of the pci address. pci address bits [31:24] are 0. a configuration read or write command code is output with the address during the pci address cycle (refer to table 4-44). for writes, local data is loaded into the write fifo and readyo# is returned. for reads, pci 9080 holds off readyo# while gathering an lword from the pci bus. example 1 to perform a type 0 configuration cycle to pci device on ad[21]. 1. pci 9080 must be configured to allow direct master access to the pci buses. pci 9080 must also be set to respond to i/o space accesses. these bits must be set in (loc:04h): ? field 0 = i/o space = 1 ? field 2 = master enable = 1 2. direct master range is selected by the board designer. for this example, use a range of 1 mb: ? 1 mb = 2 20 = 000fffffh value to program into the range register is the inverse of 000fffffh, which is fff00000h: ? (loc:9ch) = fff00000h 3. local base address for direct master to pci io/cfg is determined by the board designer. for this example, use 40000000h: ? (loc:a4h) = 40000000h 4. pci address (remap) for direct master to pci memory register must enable direct master i/o access. this bit must be set in (loc:a8h): ? field 1 = direct master i/o access enable = 1 5. pci must know which pci device and pci configuration register the pci configuration cycle is accessing. for this example, access the pci device on ad[21]. also access the pci base address 0 for memory mapped configuration register (pci:10h). (pci:10h) is the fourth register, counting from 0 (use table 4-5, pci configuration registers, for reference). these bits must be set in (loc:ach): ? fields 1:0 = configuration type 0 = 00b ? fields 7:2 = register number = the fourth register, and therefore must program a 4 into this field, beginning with bit 2 = 000100b ? fields 10:8 = function number = 000b ? fields 15:11 = device number = n-11, where n is the value in ad[n]=21-11 = 10 = 01010b ? fields 23:16 = bus number = 00000000b ? field 31 = configuration enable = 1
section 3 pci 9080 functional description ? plx technology, inc., 1997 page 21 version 1.02 the register number (bits [7:2]) or device number (bits [15:11]) must be modified and a new cft read/write cycle must be performed before other registers or devices can be accessed. 3.6.1.7 direct bus master lock pci 9080 supports direct local to pci bus exclusive accesses (locked atomic operations). a locked operation must start with the local bus input llock# being asserted during a direct master bus read cycle. refer to the timing in section 8, timing diagrams. 3.6.1.8 master/target abort pci 9080 master/target abort logic enables a local bus master to perform a direct master bus poll of devices to determine whether the devices exist (typically when the local bus performs configuration cycles to the pci bus). if a pci master, target abort, or retry time-out is encountered during a transfer, pci 9080 asserts lserr# if enabled (refer to intcsr[1:0], table 4-58) (can be used as an nmi). if the local bus master is waiting for a readyo#, it is asserted along with btermo#. the local masters interrupt handler can take the appropriate application specific action. it can then clear the abort bits in the pci status configuration register (refer to table 4-12) of the pci 9080 to clear the lserr# interrupt and re-enable direct master transfers. if a local bus master is attempting a burst read from a nonresponding pci device (master/target abort), it receives the readyo# and btermo# for the first cycle only. if the local processor cannot terminate its burst cycle, it may cause the local processor to hang. the local bus must then be reset from the pci bus or by a local watchdog timer asserting reseti#. if the local bus master cannot terminate its cycle with btermo#, it should not perform burst cycles when attempting to determine whether a pci device exists. 3.6.1.9 write and invalidate pci 9080 can be programmed to perform write and invalidate cycles to the pci for dma and direct master transfers. pci 9080 supports write and invalidate transfers for cache line sizes of 8 or 16 lwords. the size is specified in the pci cache line size register. if a size other than 8 or 16 is specified, pci 9080 performs write transfers rather than write and invalidate transfers. 3.6.1.9.1 dma write and invalidate dma write and invalidate transfers are enabled when the write and invalidate enable bit of a dma controller is set in its mode register and the memory write and invalidate enable bit is set in the pci command register. in write and invalidate mode, pci 9080 waits until the number of lwords required for the specified cache line size have been read from the local bus before starting the pci access. this ensures that a complete cache line write can be completed in one pci bus ownership. if a target disconnects before a cache line is completed, pci 9080 completes the remainder of that cache line using normal writes before resuming write and invalidate transfers. if a write and invalidate cycle is in progress, pci 9080 continues to burst if another cache line has been read from the local bus before the cycle completes. otherwise, pci 9080 terminates the burst and waits for the next cache line to be read from the local bus. if the final transfer is not a complete cache line, pci 9080 completes dma transfer using normal writes. 3.6.1.9.2 direct master write and invalidate direct master write and invalidate transfers are enabled when the invalidate enable bit is set in the pci base address (remap) register for direct master to pci memory and the memory write and invalidate enable bit is set in the pci command register (refer to table 4- 11). in write and invalidate mode, if the start address of the direct maser transfer is on a cache line boundary, pci 9080 waits until the number of lwords required for specified cache line size have been written from the local bus before starting pci write and invalidate access. this ensures that a complete cache line write can be completed in one pci bus ownership. if the start address is not on a cache line boundary, pci 9080 starts a normal pci write access. pci 9080 terminates a cycle at a cache line boundary if it is performing a normal write or if it is performing a write and invalidate cycle and another cache line of data is not available. if an entire cache line is available by the time the pci 9080 regains use of the pci bus, pci 9080 resumes write and invalidate cycles. otherwise, it continues with a normal write. if a target disconnects before a cache line is completed, pci 9080 completes the remainder of that cache line using normal writes.
section 3 pci 9080 functional description ? plx technology, inc., 1997 page 22 version 1.02    
         
     
 
 
   

  
 
  
   

 
  
 
   

  
 
     
 

 
 
     

 


  
    
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section 3 pci 9080 functional description ? plx technology, inc., 1997 page 23 version 1.02 3.6.2 direct slave operation (pci master to local bus access) pci 9080 supports both burst memory mapped transfer accesses and i/o-mapped, single-transfer accesses to the local bus from the pci bus. pci base address registers are provided to set up the location of the adapter in pci memory and i/o space. in addition, local mapping registers allow address translation from pci address space to local address space. there are three spaces available: ? space 0 ? space 1 ? expansion rom space expansion rom space is intended to support a bootable rom device for the host. each local space can be programmed to operate 8 bit, 16 bit, or 32 bit local bus width. pci 9080 has an internal wait state generator and external wait state input (readyi#). readyi# can be disabled or enabled with the internal configuration register. the local bus, independent of the pci bus, can ? burst as long as data is available (continuous burst mode) ? burst four lwords at a time ? perform continuous single cycle, with or without wait state(s) for single cycle direct slave reads, pci 9080 reads a single local bus lword or partial lword. pci 9080 disconnects after one transfer for all direct slave i/o accesses. for the highest data transfer rate, pci 9080 supports posted write and can be programmed to prefetch data during pci burst read. the prefetch size, when enabled, can be one to 16 lwords, or until the pci stops requesting. pci 9080 will prefetch if enabled and drop the local bus after the prefetch counter is reached. in a continuous prefetch mode, pci 9080 prefetches as long as any fifo space is available and terminates the prefetch when the pci terminates the request. if read prefetching is disabled, pci 9080 disconnects after one read transfer. 3.6.2.1 pci 2.1 mode pci 9080 can be programmed through the local arbitration and pci mode register to perform delayed reads, as specified in pci specification v2.1.  
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section 3 pci 9080 functional description ? plx technology, inc., 1997 page 24 version 1.02 case when the local bus latency timer is enabled and expires. (refer to figure 3-11 and figure 3-12.)   ; >; ,< ;  -.
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   figure 3-12. direct slave read for direct slave reads, the pci (master) reads data from the local bus (slave). pci 9080 supports on-the-fly endian conversion for space 0, space 1, and expansion rom space. the local bus can be big/little endian by either using the bigend# input pin or the programmable internal register configuration. when bigend# is asserted, it overwrites the internal register configuration. note: pci bus is always little endian. 3.6.2.2 pci to local address mapping note: not applicable if i 2 o mode. three local address spacesspace 0, space 1, and expansion romare accessible from the pci bus. each is defined by a set of three registers: ? local address range ? local base address ? pci base address a fourth register, bus region descriptor register for pci to local accesses, defines the local bus characteristics for both regions. (refer to figure 3-13.) 3.6.2.2.1 byte enables lbe[3:0]# (pins 139-142) are encoded based on the configured bus width, as follows: 32-bit bus for a 32-bit bus, the four byte enables indicate which of the four bytes are active during a data cycle. ? be3# byte enable 3ld[31:24] ? be2# byte enable 2ld[23:16] ? be1# byte enable 1ld[15:8] ? be0# byte enable 0ld[7:0] 16-bit bus for a 16-bit bus, be3#, be1# and be0# are encoded to provide bhe#, la1, and ble#, respectively. ? be3# byte high enable (bhe#)ld[15:8] ? be2# not used ? be1# address bit 1 (la1) ? be0# byte low enable (ble#) ld[7:0] 8-bit bus for an 8-bit bus, be1# and be0# are encoded to provide la1 and la0, respectively. ? be3# not used ? be2# not used ? be1# address bit 1 (la1) ? be0# address bit 0 (la0) each pci to local address space is defined as part of reset initialization as described in the next section.
section 3 pci 9080 functional description ? plx technology, inc., 1997 page 25 version 1.02 3.6.2.2.2 local bus initialization software range specifies which pci address bits to use for decoding a pci access to local bus space. each of the bits corresponds to a pci address bit. bit 31 corresponds to address bit 31. write a value of 1 to all bits that must be included in decode and a 0 to all others. remap pci to local addresses into a local address space bits in this register remap (replace) the pci address bits used in decode as the local address bits. local bus region descriptor specifies the local bus characteristics. 3.6.2.2.3 pci initialization software pci reset software determines how much address space is required by writing a value of all ones (1) to a pci base address register and then reading back the value. pci 9080 return zeroes in dont care address bits, effectively specifying the address space required. the pci software then maps the local address space into the pci address space by programming the pci base address register. (refer to figure 3-13.)    
         
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section 3 pci 9080 functional description ? plx technology, inc., 1997 page 26 version 1.02 example 2 a 1 mb local address space 12300000h through 123fffffh is accessible from the pci bus at pci addresses 78900000h through 789fffffh. a. local initialization software sets the range and local base address registers as follows: ? range fff00000h (1 mb, decode the upper 12 pci address bits) ? local base address (remap) 123xxxxxh (local base address for pci to local accesses) (bit 0, the space enable bit, must be set to 1 to be recognized by the host) b. pci initialization software writes all ones to the pci base address, then reads it back again. ? pci 9080 returns a value fff00000h. the pci software then writes to pci base address register ? pci base address 789xxxxxh (pci base address for access to local address space) for pci direct access to the local bus, pci 9080 has a 32 lword (128 byte) write fifo and a 16 lword (64 byte) read fifo. fifos enable the local bus to operate independently of the pci bus. pci 9080 can be programmed to return a retry response or to throttle trdy# for any pci bus transaction attempting to write to the pci 9080 local bus when the fifo is full. for pci read transactions from the pci 9080 local bus, pci 9080 holds off trdy# while gathering the local bus lword to be returned. for read accesses mapped to the pci memory space, pci 9080 prefetches up to 16 lwords (has continuous prefetch mode) from the local bus. unused read data is flushed from the fifo. for read accesses mapped to the pci i/o space, pci 9080 does not prefetch read data. rather, it breaks each read of the burst cycle into a single address/data cycle on the local bus. the period of time the pci 9080 holds off trdy# can be programmed, target retry timer, in the local bus region descriptor register (refer to table 4-39). pci 9080 issues a retry to the pci bus transaction master when the programmed time period expires. this occurs when the pci 9080 cannot gain control of the local bus and return trdy# within the programmed time period. 3.6.2.3 deadlock and breqo a deadlock situation can occur when a master on the pci bus wants to access the pci 9080 local bus at the same time a master on the local pci 9080 bus wants to access the pci bus. two types of deadlock situations can occur: ? partial deadlock a master on the local bus is performing a direct bus master access to a pci bus device other than the pci bus device that is concurrently trying to access the local bus. ? full deadlock a master on the local bus is performing a direct bus master access to the same pci bus device that is concurrently trying to access the local bus. this applies only to direct (pass through) master and slave accesses through the pci 9080. deadlock will not occur in transfers through the pci 9080 dma controller or the mailboxes. for partial deadlock, the pci access to the local bus times out (the target retry timer, which is programmable through the local bus region descriptor register for pci to local accesses) and the pci 9080 responds with a pci retry. pci specification requires that a pci master release its request for the pci bus (de-asserts req#) for a minimum of two pci clocks after receiving a retry. this allows the pci bus arbiter to grant the pci bus to the pci 9080 so that it can complete its direct master access and free up the local bus. possible solutions are described below for cases in which the pci bus arbiter does not function as described (pci bus architecture dependent), waiting for a time-out is undesirable, or a full deadlock condition exists. for full deadlock, the only solution is to back off the local master. 3.6.2.3.1 backoff pci 9080 contains a pin (breqo) that indicates a possible deadlock condition exists. pci 9080 starts the breqo timer (programmable through registers) when it detects the following conditions: ? a master on the pci bus is trying to access memory or an i/o device on the local bus and is not gaining access (for example, lholda not received). ? a master on the local bus is performing a direct bus master read access to the pci bus or a master on the local bus is performing a direct bus master write access to the pci bus and the pci 9080s direct master write fifo cannot accept another write cycle.
section 3 pci 9080 functional description ? plx technology, inc., 1997 page 27 version 1.02 if timer expires and pci 9080 has not received lholda, pci 9080 asserts breqo. external bus logic can use this as a signal to perform backoff. a backoff cycle is device/bus architecture dependent. external logic (arbiter) can assert the necessary signals to cause the local master to release the local bus (backoff). after backing off the local master, it can grant the bus to the pci 9080 (by asserting lholda). once breqo is asserted, readyo# for the current data cycle will never be asserted (the local bus master must perform backoff). when the pci 9080 detects lholda, it proceeds with the pci master to local bus access. when this access is complete and the pci 9080 releases the local bus, the external logic can release backoff and the local master can resume the cycle that was interrupted by the backoff cycle. the write fifo of the pci 9080 retains all the data it has acknowledged (i.e. the last data for which readyo# was asserted). after the backoff condition ends, the local master restarts the last cycle with ads#. for writes, the data following this ads# should be the data that was not acknowledged by the pci 9080 prior to the backoff cycle (for instance, the last data for which there was no readyo# asserted). if a pci read cycle is completed when the local bus is backed off, the local bus master receives that data if local master restarts the same last cycle. (data is not read twice). a new read is performed, if the resumed local bus cycle is not the same as the backed off cycle. 3.6.2.3.2 software/hardware solution for systems without backoff capability for adapters that do not support backoff, a possible deadlock solution is as follows. pci host software, external local bus hardware, general purpose output usero and general purpose input (useri) can be used by pci host software to prevent deadlock. usero can be set to request that the external arbiter not grant the bus to any local bus master except the pci 9080. a status output from the local arbiter can be connected to general purpose input useri to indicate that no local bus master owns the local bus. the input can be read by the pci host to determine that no local bus master currently owns the local bus. pci host can then perform a direct slave access. when the host is done, it clears usero. for devices that support preempt, usero can be used to preempt the current bus master device. the current local bus master device completes its current cycle and gives up the local bus (de-asserts lhold). 3.6.2.3.3 software solutions to deadlock pci host software and local bus software can use a combination of mailbox registers, doorbell registers, interrupts, direct local to pci accesses and direct pci to local accesses to avoid deadlock. 3.6.2.4 direct slave lock pci 9080 supports direct pci to local bus exclusive accesses (locked atomic operations). a pci locked operation to local bus results in the entire address space 0, space 1 and expansion rom space being locked until they are released by the pci bus master. pci 9080 asserts llocko# during the first clock of an atomic operation (address cycle) and de-asserts it a minimum of one clock, following the last bus access for the atomic operation. llocko# is de-asserted after the pci 9080 detects pci frame# and pci lock# de-asserted at the same time. refer to the timing diagrams in section 8, timing diagrams. locked operations are enabled or disabled with the local bus region descriptor register for pci to local accesses. it is the responsibility of external arbitration logic to monitor the llocko# pin and enforce the meaning for an atomic operation. for example, if a local master initiates a locked operation, the local arbiter may choose to not grant use of the local bus to other masters until the locked operation is complete. 3.6.3 direct slave priority direct slave accesses have higher priority than dma accesses. direct slave accesses preempt dma transfers. when the pci 9080 dma controller owns the local bus, its lhold output and lholda input are asserted and its ldshold output is de-asserted. when a direct slave access occurs, pci 9080 gives up the local bus within two lword transfers by de-asserting lhold and floating its local bus outputs. after the pci 9080 samples its lholda input de-asserted, it requests the local bus for a direct slave transfer by asserting lhold and ldshold. when the pci 9080 receives lholda, it drives the bus and performs the direct slave transfer. upon completion of the direct slave transfer, pci 9080 gives up the local bus by de-asserting both lhold and ldshold and floating its local bus outputs. after the pci 9080 samples its lholda de-asserted and its local pause timer is zero, it requests the local bus for a dma transfer by re-asserting lhold. when it receives lholda, it drives the bus and continues with the dma transfer.
section 3 pci 9080 functional description ? plx technology, inc., 1997 page 28 version 1.02 3.7 dma operation pci 9080 supports two independent dma channels capable of transferring data from the local bus to the pci bus or from the pci bus to the local bus. each channel consists of a dma controller and a programmable fifo. both channels support chaining and non-chaining transfers, demand mode dma, and end of transfer (eot) pins. master mode must be enabled in the pci command register. 3.7.1 non-chaining mode dma the host processor or the local processor sets the local address, pci address, transfer count and transfer direction. the host or local processor then sets a control bit to initiate the transfer. pci 9080 will arbitrate the pci and local buses and transfer data. once the transfer is complete, pci 9080 sets the channel done bit to a value of 1 and generates an interrupt to the local processor or the pci host (programmable). dma done bit in the internal dma register can be pooled to indicate the status of dma transfer. dma registers are accessible from the pci bus and local bus. (refer to figure 3-14.)     !" # $  % & !" # $  % &    &    &&     &&     + ,-  !    '     &  -!  &.    ' ! !  () 

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section 3 pci 9080 functional description ? plx technology, inc., 1997 page 29 version 1.02 the local processor or pci requires dma. pci 9080 is master on both the pci and local buses. direct slave or direct master pre-empts dma. pci 9080 releases the pci bus if one of the following occurs (refer to figure 3-15): ? fifo full ? terminal count reached ? pci latency timer (pci:0dh)(loc:0dh) expires (refer to table 4-16[7:0])normally programmed by the host pci bios and pci gnt# de-asserts ? pci host asserts stop ? direct master request pending     
     
    
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   '   * *  figure 3-16. dma, local to pci 3.7.2 chaining mode dma in chaining mode dma, the host processor or the local processor sets up descriptor blocks in local or host memory that are composed of a pci address, local address, transfer count, transfer direction, and address of the next descriptor block (refer to figure 3-18). host or local processor then sets up the address of the initial descriptor block in the descriptor pointer register of the pci 9080 and initiates the transfer by setting a control bit. pci 9080 loads the first descriptor block and initiates the data transfer. pci 9080 continues to load descriptor blocks and transfer data until it detects the end of chain bit is set in the next descriptor pointer register. pci 9080 can be programmed to interrupt the local processor by setting the "interrupt after terminal count" bit or pci host upon completion of each block transfer and after all block transfers are complete (done) (refer to figure 3-17). if chaining descriptors are located in local memory, the dma controller can be programmed to clear the transfer size at the completion of each dma. (refer to dma clear count mode, table 4-62[16] and table 4-67[16].) notes: in chaining mode dma, the descriptor includes pci address, local address, transfer size and the next descriptor pointer. (pci:84h, location 104-pci:90h, location 110d). the descriptor pointer register contains the end of chain bit, direction of transfer, next descriptor address, and next descriptor location. dma descriptor can be on the local memory or pci memory, or both (first descriptor on local memory, and second descriptor on pci memory).
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section 3 pci 9080 functional description ? plx technology, inc., 1997 page 32 version 1.02 3.7.3.2 pci to local bus dma transfer  
    
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(    (         !     #  &  !   (  )   ( 3 &  !  figure 3-20. pci to local bus dma data transfer operation 3.7.3.3 unaligned transfers for unaligned local to pci transfers, pci 9080 reads a partial lword from the local bus. it continues to read lwords from the local bus. lwords are assembled, aligned to the pci bus address and loaded into the fifo. for pci to local transfers, lwords are read from the pci bus and loaded into the fifo. on the local side, the lwords are assembled from the fifo, aligned to the local bus address and written to the local bus. on both the local and pci buses, the byte enables for writes determine la[1:0] for the start of a transfer. for the last transfer, the byte enables specify the bytes to be written. all reads are lwords. 3.7.4 demand mode dma dma mode register bit 15 (blast mode for demand mode dma), determines the number of lwords transferred after a dma controllers dreq[1:0]# input is de-asserted. if blast# output is not required for the last lword of the dma transfer (bit 15 = 1), the dma controller releases the data bus after it receives an external readyi# or the internal wait state counter decrements to a value of 0 for the current lword. if dma controller is currently bursting data, which is not the last data phase for the burst, blast# output will not be asserted. if blast# output is required for the last lword of the dma transfer (bit 15 = 0), the dma controller transfers one or two lwords. if dreq[1:0]# is de-asserted during the address phase of the first transfer in a pci 9080 local bus ownership (ads#, lholda asserted), the dma controller completes the current lword. if dreq[1:0]# is de-asserted during any phase other than the address phase of the first transfer in a pci 9080 local bus ownership, the dma controller completes the current lword, and one additional lword (this allows blast# output to be asserted during the final lword). if dma fifo is full/empty after the data phase in which
section 3 pci 9080 functional description ? plx technology, inc., 1997 page 33 version 1.02 dreq[1:0]# is de-asserted, the second lword is not transferred. dreq[1:0]# controls only the number of lword transfers. for an 8-bit bus, pci 9080 gives up the bus after the last byte for the lword is transferred. for a 16-bit bus, pci 9080 gives up the bus after the last word for the lword is transferred. 3.7.5 dma priority dma channel 0 priority, dma channel 1 priority, or rotating priority can be specified in the dma arbitration register. 3.7.6 dma arbitration pci 9080 dma controller releases control of the local bus (de-asserts lhold) when one of the following occurs: ? fifos are full in a local to pci transfer ? fifos are empty in a pci to local transfer ? local bus latency timer expires (if enabled) ? breq input is asserted (breq can be enabled or disabled, or gated with a latency timer before the pci 9080 gives up the local bus) ? direct slave access is pending ? eot input is received (if enabled) dma controller releases control of the pci bus when one of the following occurs: ? fifos are full or empty ? pci latency timer expires and loses the pci grant signal ? target disconnect response received dma controller de-asserts its pci bus request (req#) for a minimum of two pci clocks. 3.7.6.1 end of transfer (eot0# or eot1#) input dma mode register bit 14 (blast mode for eot), determines the number of lwords transferred after a dma controller eot[1:0]# input is asserted. if blast# output is not required for the last lword of the dma transfer (bit 14 = 1), the dma controller releases the data bus and terminates dma after it receives an external readyi# or the internal wait state counter decrements to a value of 0 for the current lword. if the dma controller is currently bursting data, which is not the last data phase for the burst, blast# output will not be asserted. if blast# output is required for the last lword of the dma transfer (bit 14 = 0), the dma controller transfers one or two lwords. if eot[1:0]# is asserted, the dma controller completes the current lword, and one additional lword (this allows blast# output to be asserted during the final lword). if dma fifo is full/empty after the data phase in which eot[1:0]# is asserted, the second lword is not transferred. dma controller terminates a transfer on an lword boundary after eot[1:0]# is asserted. for an 8-bit bus, pci 9080 terminates after the last byte for the lword is transferred. for a 16-bit bus, pci 9080 terminates after the last word for the lword is transferred. 3.7.6.2 dma abort a dma transfer can be aborted. the abort process is as follows: 1. dma channel must be enabled (table 4-72[0]=1). 2. dma channel must be started (table 4-72[1]=1). 3. wait for the channel done bit to be set to zero (table 4-72[4]=0). 4. disable the dma channel (table 4-72[0] =0). 5. abort dma by programming the channel abort bit (table 4-72[2]=1). 6. wait until the channel done bit is set (table 4- 72[4]=1). note: one to two data transfers occur after the abort bit is set. aborting when no dma cycles are in progress causes the next dma to abort. 3.7.6.3 local latency and pause timers a local bus latency timer and local bus pause timer are programmable with the dma arbitration register. if local latency timer expires, pci 9080 completes the current lword transfer and releases lhold. after its programmable pause timer expires, it reasserts lhold. when it receives lholda, it continues the transfer. pci bus transfer continues until the fifo is empty for a local to pci transfer or until it is full for a pci to local transfer.
section 3 pci 9080 functional description ? plx technology, inc., 1997 page 34 version 1.02 3.8 vendor and device id registers three vendor and device id registers are supported: ? (loc:00h), which contains the normal device and vendor ids. this register can be loaded from the serial eeprom or from local processors. ? (loc:2ch), which contains the subsystem and subvendor ids. this register can be loaded from the serial eeprom or from local processors. ? (loc:f0h), which contains the hardcoded plx vendor and device ids. 3.9 doorbell registers there are two 32 bit doorbell interrupt/status registers in the pci 9080. one is assigned to the pci bus interface and the other is assigned to the local bus interface. the local processor can generate a pci bus interrupt by writing any number other than all zeroes to the pci to local doorbell register (refer to table 4-56). a pci host can generate a local bus interrupt by writing any number other than all zeroes to the local to pci doorbell register (refer to table 4-57). 3.10 mailbox registers there are eight 32 bit mailbox registers in the pci 9080 that can be written to and read from both buses. these registers can be used to pass command and status information directly between local and pci bus devices. a local interrupt can be generated, if enabled, when the pci host writes to one of the first four mailbox registers. 3.11 user input and output pci 9080 supports user input and output pins, useri (pin 31) and usero (pin 27), respectively. user output data can be logged by writing to bit 16 of (loc:ech). user input data can be read from bit 17. (refer to table 4-59.)
section 3 pci 9080 functional description ? plx technology, inc., 1997 page 35 version 1.02 3.12 interrupts linto# dma ch 0 done dma ch 1 done doorbells mailboxes bist messaging queue x9 x4 [17] [7] [23] x2 or x3 x8 x6 or x7 or dma ch 1 terminal count lserr# master abort 256 retrys target abort parity error messaging queue doorbells master abort 256 retrys target abort linti# messaging queue [1] [0] x1 or [12] or [9] [10] [11] or [12] or x5 inta# dma ch 0 done dma ch 0 terminal count x4 x2 or x3 dma ch 1 done x8 x6 or x7 dma ch 1 terminal count dma ch 0 terminal count [8] [16] the # represent the bit # of register (loc [e8h]) x1 = bits [7:6] of register (loc [168h]) x2 = bit 10 of register (loc [100h]) x3 = bit 2 of register (loc [e110h]) x4 = bit 18 of register (loc [e8h]) & bit 17 of register (loc [100h]) x5 = bits [5:4] of register (loc [168h]) x7 = bit 2 of register (loc [124h]) x6 = bit 10 of register (loc [114h]) x8 = bit 19 of register (loc [e8h]) and bit 17 of register (loc [114h]) x9 = bit 3 of register (loc [b0h]) & bit 3 of register (loc [b4h]) for x4 and x8, if bit 17='0', then linto# is generated and if bit 17='1', then inta# is generated. figure 3-21. interrupt and error sources 3.12.1 pci interrupts (inta#) a pci 9080 pci interrupt (inta#) can be generated by one of the following: ? local to pci doorbell register ? local interrupt input ? master/target abort status condition ? dma ch 0/ch 1 done ? dma ch 0/ch 1 terminal count reached ? messaging outbound post queue not empty inta#, or individual sources of an interrupt, can be enabled or disabled with the pci 9080 interrupt control/status register (refer to table 4-58). this register also provides interrupt status for each interrupt source. pci 9080 pci bus interrupt is level output. an interrupt can be cleared by disabling an interrupt enable bit or clearing the cause(s) of the interrupt. 3.12.1.1 local interrupt input asserting local bus input pin linti# can generate a pci bus interrupt. pci host processor can read pci 9080 interrupt control/status register to determine that an interrupt is pending due to the linti# pin being asserted. the interrupt remains asserted as long as the linti# pin is asserted and the local interrupt input is enabled. adapter specific action can be taken by the pci host processor to cause the local bus to release linti#. 3.12.1.2 master/target abort interrupt pci 9080 sets the master abort or target abort status bit in the pci configuration register when it detects a master or target abort. these status bits cause pci inta# to be asserted if interrupts are enabled. the interrupt remains asserted as long as the master or target abort bits remain set in the pci status configuration register (refer to table 4-12) and master/target abort interrupt is enabled. use a pci type 0 configuration access or a local access to clear the
section 3 pci 9080 functional description ? plx technology, inc., 1997 page 36 version 1.02 master abort and target abort interrupt bits in the pci status configuration register. bits [26:24] of the interrupt control/status register (refer to table 4-58) are latched at the time of a target abort interrupt or master abort interrupt. they provide information as to who was master when an abort occurred. pci 9080 updates these bits whenever an abort occurs. 3.12.2 local interrupts (linto#) a pci 9080 local interrupt (linto#) can be generated by one of the following: ? pci to local doorbell/mailboxes register access ? pci bist interrupt, the dma done interrupt ? dma terminal count is reached ? dma abort interrupt or messaging outbound post queue not empty linto#, or individual sources of an interrupt, can be enabled or disabled with the pci 9080 interrupt control/status register (refer to table 4-58). interrupt control/status register also provides interrupt status for each source of the interrupt. pci 9080 local interrupt is a level output. an interrupt can be cleared by disabling the interrupt enable bit of a source or by clearing the cause of an interrupt. 3.12.2.1 local to pci doorbell interrupt a local bus master can generate a pci bus interrupt by writing to the local to pci doorbell register (refer to table 4-57). pci host processor can then read pci 9080 interrupt control/status register (refer to table 4-58) to determine that a doorbell interrupt is pending. it can then read the pci 9080 local to pci doorbell register. each bit in the local to pci doorbell register is individually controlled. bits in the doorbell register can only be set by the local side. from the local side, writing a 1 to any bit position sets that bit and writing a 0 to a bit position has no effect. bits in the local to pci doorbell register can only be cleared from the pci side. from the pci side, writing a 1 to any bit position clears that bit and writing a 0 to a bit position has no effect. the interrupt remains asserted as long as any of the local to pci doorbell register bits are set and pci doorbell interrupt is enabled. to prevent race conditions when the pci bus is accessing the doorbell register (or any configuration register), pci 9080 automatically de-asserts readyo# to prevent local bus accesses. 3.12.2.2 pci to local doorbell interrupt a pci bus master can generate a local bus interrupt by writing to the pci to local doorbell register (refer to table 4-56). local processor can then read the pci 9080 interrupt control/status register (refer to table 4- 58) to determine that a doorbell interrupt is pending. it can then read the pci 9080 pci to local doorbell register. each bit in the pci to local doorbell register is individually controlled. bits in the doorbell register can only be set by the pci side. from the pci side, writing 1 to any bit position sets that bit and writing 0 to a bit position has no effect. bits in the pci to local doorbell register can only be cleared from the local side. from the local side, writing 1 to any bit position clears that bit and writing 0 to a bit position has no effect. note: if local side cannot clear doorbell interrupt, do not use the pci to local doorbell register. the interrupt remains asserted as long any of the pci to local doorbell register bits are set and the local doorbell interrupt is enabled. to prevent race conditions when the local bus is accessing the doorbell register (or any configuration register), pci 9080 automatically issues a retry to the pci bus. 3.12.2.3 built-in self test interrupt (bist) a pci bus master can generate a local bus interrupt by performing a pci type 0 configuration write to a bit in the pci bist register. the local processor can then read the pci 9080 interrupt control/status register (refer to table 4-58) to determine that a bist interrupt is pending. the interrupt remains asserted as long as the bit is set and the bist interrupt is enabled. the local bus then resets the bit when bist is complete. pci host software may fail the device if the bit is not reset after two seconds. note: pci 9080 does not have internal bist. 3.12.2.4 dma channel 0/1 interrupts a dma channel can generate a pci or local bus interrupt when done (transfer complete) or after a transfer is complete for a descriptor in chaining mode. a bit in the dma mode register determines whether to generate a pci or local interrupt. the local or pci processor can then read the pci 9080 interrupt control/status register (refer to table 4-58) to determine whether a dma channel interrupt is pending.
section 3 pci 9080 functional description ? plx technology, inc., 1997 page 37 version 1.02 a done status bit in the control/status register can be used to determine whether the interrupt is ? a done interrupt ? the result of a transfer for a descriptor in a chain that is not yet complete mode register of a channel enables a done interrupt. in chaining mode, a bit in the next descriptor pointer register of the channel (loaded from local memory) specifies whether to generate an interrupt at the end of the transfer for the current descriptor. a dma channel interrupt is cleared by writing a 1 to the clear interrupt bit in the dma command/status register (refer to table 4-72[3] and table 4-73[3]). 3.12.3 pci serr# (pci nmi) pci 9080 generates an serr# pulse if parity checking is enabled in the pci command register and it detects an address parity error or the generate serr# bit in the interrupt control/status register (refer to table 4-58) is 0 and a 1 is written. serr# output can be enabled or disabled with pci command register. 3.12.4 local lserr# (local nmi) lserr# interrupt output is asserted if the following occurs: ? pci bus target abort or master abort status bit is set in the pci status configuration register ? parity error status bit is set in the pci status configuration register ? messaging outbound free queue overflows if parity error checking is enabled in the pci command register, pci 9080 sets the master detected parity error status bit in the pci status configuration register (refer to table 4-12) if it detects one of the following: ? parity error during a pci 9080 master read ? pci bus signal perr# being asserted during a pci 9080 master write pci 9080 sets a parity error bit in the pci status configuration register (refer to table 4-12) if it detects one of the following: ? data parity error during a pci 9080 master read ? data parity error during a slave write access to the pci 9080 ? address parity error the pci 9080 interrupt control/status register (refer to table 4-58) can be used to individually enable or disable lserr# for an abort or parity error. lserr# is a level output that remains asserted as long as the abort or parity error status bits are set. 3.13 i 2 0 compatible message unit messaging unit supplies two paths for messages, two inbound fifos to receive messages from the primary pci bus and two outbound fifos to pass messages to the primary pci bus. refer to i 2 o architecture specification v1.5 for details. figure 3-22 and figure 3-23 illustrate information about the i 2 0 architecture. +     &!       $ ,   - $    
    
    
        
 
   
 
         
     figure 3-22. i 2 o system architecture  
  
     

  
                               figure 3-23. i 2 o software architecture
section 3 pci 9080 functional description ? plx technology, inc., 1997 page 38 version 1.02 3.13.1 inbound messages inbound messages reside in a pool of message frames (minimum 64-byte frames) allocated in shared local bus (iop) memory. the inbound message queue is comprised of a pair of rotating fifos implemented in local memory. inbound free list fifo holds the message frame addresses (mfa) of available message frames in local memory. inbound post list fifo holds the mfa of all currently-posted messages. the inbound circular fifos are accessed by external pci agents through inbound queue port location in the pci address space. inbound queue port, when read by an external pci agent, returns the inbound free list fifo mfa. an external pci agent places a message frame into the inbound post list fifo by writing its mfa to the inbound queue port location. 3.13.2 outbound messages outbound messages reside in a pool of message frames (minimum 64-byte frames) allocated in shared pci bus (host system) memory. the outbound message queue is comprised of a pair of rotating fifos implemented in local memory. outbound free list fifo holds the message frame addresses (mfa) of available message frames in system memory. outbound post list fifo holds the mfa of all currently posted messages. the outbound circular fifos are accessed by external pci agents through the outbound queue port location in the pci address space. outbound queue port, when read by an external pci agent, returns the outbound post list fifo mfa. an external pci agent places free message frames into the outbound free list fifo by writing the free mfa into the outbound queue port location. memory for the circular fifos themselves must be allocated in local (iop) memory. the queues base address is contained in queue base address register (qbar). each fifo entry is a 32 bit data value. each read and write of the queue must be a single 32-bit access. the circular fifos range in size from 4k entries to 64k entries. all four fifos must be the same size and contiguous. therefore, the total amount of local memory needed for circular fifos ranges from 64 kb to 1 mb. fifo size is specified in the messaging queue configuration register (mqcr) (refer to table 4-79). the starting address of each fifo is based on the queue base address and the fifo size, as listed in table 3-7. table 3-7. queue starting address fifo starting address inbound free list qbar inbound post list qbar + (1 * fifo size) outbound post list qbar + (2 * fifo size) outbound free list qbar + (3 * fifo size) 3.13.3 i 2 o pointer management fifos always reside in shared local (iop) memory and are allocated and initialized by the iop. before enabling i 2 o (messaging queue configuration register bit 0 set to 1), the local processor must initialize the inbound post and free head pointer registers, the inbound post and free tail pointer registers, the outbound post and free head pointer registers, and the outbound post and free tail pointer registers with the initial offset according to the configured fifo size. messaging unit automatically adds the queue base address to offset in each head and tail pointer register. the software can then enable i 2 o. after initialization, the local software should not write to the pointers managed by the mu hardware. the empty flags are set if the queues are disabled (mqcr bit 0 = 0) and head and tail pointers are equal. this occurs independently of how the head and tail pointers are set. an empty flag is cleared, signifying not empty, only if the queues are enabled and pointers become not equal. if an empty flag is cleared and the queues are enabled, the empty flag will only be set if the tail pointer is incremented and head and tail pointers become equal. full flags are always cleared when the queues are disabled or the head and tail pointers are not equal. a full flag is set when the queues are enabled, the head pointer is incremented, and the head and tail pointers become equal. each circular fifo has a head pointer and a tail pointer, which are offsets from the queue base address. writes to a fifo occur at the head of the fifo and reads occur from the tail. the head and tail pointers are incremented by either the local processor or the mu hardware. the unit that writes to the fifo also maintains the pointer. the pointers are incremented after fifo access. both pointers wrap around to the first address of the circular fifo when they reach the fifo size, so that the head and tail pointers chase each other around and around in the circular fifo. mu wraps the pointers automatically for the pointers that it maintains. iop software must wrap the pointers that it maintains. whenever they are equal, the fifo is empty. to prevent overflow conditions, i 2 o
section 3 pci 9080 functional description ? plx technology, inc., 1997 page 39 version 1.02 specifies that the number of message frames allocated should be less than or equal to the number of entries in a fifo. (refer to figure 3-24 for additional information.) each inbound mfa is specified by i 2 o as the offset from the start of shared local (iop) memory region 0 to the start of the message frame. each outbound mfa is specified as the offset from host memory location 0x00000000h to the start of the message frame in shared host memory. since the mfa is an actual address, the message frames need not be contiguous. iop allocates and initializes inbound message frames in shared iop memory using any suitable memory allocation technique. host allocates and initializes outbound message frames in shared host memory using any suitable memory allocation technique. message frames are a minimum of 64 bytes in length. i 2 o uses a push (write preferred) memory model. that means that the iop will write messages and data to the shared host memory, and the host will write messages and data to shared iop memory. software should make use of burst and dma transfers whenever possible to ensure efficient use of the pci bus for message passing. additional information on message passing implementation may be found in the i 2 o architecture specification v1.5 . 3.13.4 inbound free list fifo the local processor allocates inbound message frames in its shared memory and can place the address of a free (available) message frame into the inbound free list fifo by writing its mfa into the fifo location pointed to by the queue base register + inbound free head pointer register. the local processor must then increment the inbound free head pointer register. a pci master (host or another iop) can obtain the mfa of a free message frame by reading the inbound queue port address (40h of the first pci memory base address register). if fifo is empty (no free inbound message frames are currently available, head and tail pointers are equal), the mu returns a value of -1 (ffffffffh). if fifo is not empty (head and tail pointers are not equal), the mu reads the mfa pointed to by the queue base register + inbound free tail pointer register, returns its value and increments the inbound free tail pointer register. if inbound free queue is not empty, and queue prefetching is enabled (qsr register bit 3), the next entry in the fifo is read from the local bus into a prefetch register. the prefetch register then provides the data for the next pci read from this queue, thus reducing the number of pci wait states.
section 3 pci 9080 functional description ? plx technology, inc., 1997 page 40 version 1.02 outbound post list fifo head pointer tail pointer incremented by local processor incremented by pci 9080 hardware inbound post list fifo head pointer tail pointer incremented by pci 9080 hardware incremented by local processor inbound free list fifo head pointer tail pointer incremented by local processor incremented by pci 9080 hardware outbound free list fifo head pointer tail pointer incremented by pci 9080 hardware incremented by local processor outbound queue port write read external pci agent inbound queue port write read external pci agent local processor write read local processor write read low address local memory high address local memory outbound queue inbound queue figure 3-24. circular fifo operation
section 3 pci 9080 functional description ? plx technology, inc., 1997 page 41 version 1.02 3.13.5 inbound post list fifo a pci master (host or another iop) can write a message into an available message frame in shared local (iop) memory. it can then post that message by writing the message frame address (mfa) to the inbound queue port address (40h of the first pci memory base address register). when the port is written, the mu writes the mfa to the inbound post list fifo location pointed to by the queue base register + fifo size + inbound post head pointer register. after the mu writes the mfa to the inbound post list fifo, it increments the inbound post head pointer register. inbound post tail pointer register points to the inbound post list fifo location which holds the mfa of the oldest posted message. the tail pointer is maintained by the local processor. after a local processor reads the oldest mfa, it can remove the mfa from the inbound post list fifo by incrementing the inbound post tail pointer register. pci 9080 generates a local interrupt when the inbound post list fifo is not empty. inbound post list fifo interrupt bit in the queue status/control register (qsr) indicates interrupt status. the interrupt clears when the inbound post list fifo is empty. the interrupt can be masked by the inbound post list fifo interrupt mask bit (refer to table 4-89[4]). to prevent race conditions from the time the pci write transaction is received until the data is written in local memory and the inbound post head pointer register is incremented, any pci direct slave access to the pci 9080 is issued a retry. 3.13.6 outbound post list fifo a local master (iop) can write a message into an available message frame in shared host memory. it can then post that message by writing the message frame address (mfa) to the outbound post list fifo location pointed to by the queue base register + outbound post head pointer register + (2 * fifo size). the local processor should then increment the outbound post head pointer register. a pci master can obtain the mfa of the oldest posted message by reading the outbound queue port address (44h of the first pci memory base address register). if fifo is empty (no more outbound messages are posted, head and tail pointers are equal), the mu returns a value of -1 (ffffffffh). if outbound post list fifo is not empty (head and tail pointers are not equal), the mu reads the mfa pointed to by the queue base register + (2 * fifo size) + outbound post tail pointer register, returns its value and increments the outbound post tail pointer register. pci 9080 generates a pci interrupt when the outbound post head pointer register is not equal to the outbound post tail pointer register. outbound post list fifo interrupt bit of the outbound post list fifo interrupt status (oplfis) register indicates interrupt status. when the pointers become equal, both the interrupt and the outbound post list fifo interrupt bit are automatically cleared. the pointers become equal when a pci master (host or another iop) reads enough fifo entries to empty the fifo. the interrupt can be masked by the outbound post list fifo interrupt mask (oplfim) register). 3.13.7 outbound post queue to reduce read latency, prefetching from the tail of the queue occurs whenever the queue is not empty and the tail pointer is incremented (queue has been read from), or when the queue is empty and the head pointer is incremented (queue has been written to). when the host cpu reads the outbound post queue, the data is immediately available. 3.13.8 inbound free queue to reduce read latency, prefetching from the tail of the queue occurs whenever the queue is not empty and the tail pointer is incremented (queue has been read from), or when the queue is empty and the head pointer is incremented (queue has been written to). when the host cpu reads the inbound free queue, the data is immediately available. 3.13.9 outbound free list fifo a pci master (host or another iop) allocates outbound message frames in its shared memory and can place the address of a free (available) message frame into the outbound free list fifo by writing the message frame address (mfa) to the outbound queue port address (44h of the first pci memory base address register). when the port is written, the mu writes the mfa to the outbound free list fifo location pointed to by the queue base register + (3 * fifo size) + outbound free head pointer register. after the mu writes the mfa to the outbound free list fifo, it increments the outbound free head pointer register. when the iop needs a free outbound message frame, it must first check whether any free frames are available. if outbound free list fifo is empty (outbound free head and tail pointers are equal), the iop must wait for the host to place additional outbound free message frames
section 3 pci 9080 functional description ? plx technology, inc., 1997 page 42 version 1.02 in the outbound free list fifo. if outbound free list fifo is not empty (head and tail pointers are not equal), the iop can obtain the mfa of the oldest free outbound message frame by reading the location pointed to by the queue base register + (3 * fifo size) + outbound free tail pointer register. after the iop reads the mfa, it must increment the outbound free tail pointer register. to prevent overflow conditions, i 2 o specifies that the number of message frames allocated should be less than or equal to the number of entries in a fifo. mu also checks for overflows of the outbound free list fifo. when the head pointer is incremented and becomes equal to the tail pointer, the outbound free list fifo is full, and the mu generates a local lserr (nmi) interrupt. the interrupt is recorded in the queue status control (qsr) register. from the time that the pci write transaction is received until the data is written into local memory and the outbound free head pointer register is incremented, any pci direct slave access to the pci 9080 is issued a retry. table 3-8. circular fifo summary fifo name pci port generate pci interrupt? generate local interrupt head pointer maintained by tail pointer maintained by inbound free list fifo inbound queue port (host read) no no local processor mu hardware inbound post list fifo inbound queue port (host write) no yes, when port is written mu hardware local processor outbound post list fifo outbound queue port (host read) yes, when fifo is not empty no local processor mu hardware outbound free list fifo outbound queue port (host write) no yes, (lserr) when fifo full mu hardware local processor 3.13.10 i 2 0 enable sequence to enable i 2 o, the local processor should perform the following: ? initialize space 1 address and range ? initialize all fifos and message frame memory ? set the pci class code in register (pci:09h-0bh) to be an i 2 o device with programming interface 01h ? set the i 2 o enable bit ? set the local init done bit note: nb# must be pulled up so the pci 9080 issues retries to all pci accesses until the local init done bit is set in register (loc:ech) (refer to table 4-59) by the local processor. the i 2 o enable bit in the queue status register (loc: 168h; table 4-89) causes remapping of resources for use in i 2 o mode. when this bit is set, all memory mapped configuration registers (such as queue ports 40h and 44h) and space 1 share pcibar0 (pci:10h, loc:10h; table 4-19). pci accesses to offset 00h-ffh of pcibar0 will result in accesses to the internal configuration registers of the pci 9080. accesses above offset ffh of pcibar0 will result in local space accesses beginning at offset 100h from the local space 1 remap register (las1ba, loc:174h; table 4- 46). therefore space located at offset 00h-ffh from las1ba is not addressable by way of pcibar0. programmers note: because pci accesses to offset 00h-ffh of pcibar0 result in internal configuration accesses, inbound free mfas must be greater than ffh.
section 4 pci 9080 registers ? plx technology, inc., 1997 page 43 version 1.02 4. registers 4.1 new register definitions summary refer to the descriptions in the following sections for a full explanation. table 4-1. new registers definitions summary pci offset local offset register bits description 23 add pcireqmode output. 08h or ach 88h or 12ch marbr 28 read ahead mode. 18h 98h lbrd0 15 single read mode removed. 10 extend almost full flag to five bits (fifth bit not contiguous). 11 add cdmpflimit output; do not prefetch past 4k boundary for dm. 12, 3 direct master read prefetch size control. 13 i/o remap select. 28h a8h dmpbam 15:14 direct master write delay. 30h b0h oplfis all new outbound post list fifo interrupt status register. 34h b4h oplfim all new outbound post list fifo interrupt mask register. 40h n/a iqp all new inbound queue port register. 44h n/a oqp all new outbound queue port register. 4 move dma0intsel output to dmamode0. change to reserved. 5 move dma1intsel output to dmamode1. change to reserved. 3 mailbox interrupt enable on f, not on 9060. 68h e8h intcsr 31:28 mailbox interrupts on sd, not on 9060. 16 clear byte count in chaining descriptor. 80h 100h dmamode0 17 add c0_intsel output. 0=local int., 1=pci int. 16 clear byte count in chaining descriptor. 94h 114h dmamode1 17 add c1_intsel output. 0=local int., 1=pci int. c0h 140h mqcr all new messaging queue configuration register. c4h 144h qbar all new queue base address register. c8h 148h ifhpr all new inbound free head pointer. cch 14ch iftpr all new inbound free tail pointer. d0h 150h iphpr all new inbound post head pointer. d4h 154h iptpr all new inbound post tail pointer. d8h 158h ofhpr all new outbound free head pointer. dch 15ch oftpr all new outbound free tail pointer. e0h 160h ophpr all new outbound post head pointer. e4h 164h optpr all new outbound post tail pointer. e8h 168h qsr all new i 2 o queue status register. f0h 170h las1rr all new local address space 1 range register for pci to local. f4h 174h las1ba all new local address space 1 local base address (remap). f8h 178h lbrd1 all new local address space 1 bus region descriptor.
section 4 pci 9080 registers ? plx technology, inc., 1997 page 44 version 1.02 4.1.1 register differences between pci 9080 and pci 9060, pci 9060es, and pci 9060sd table 4-2. register differences between pci 9080 and pci 9060 register pci/local offset bits description pciidr 00/00 31:16 default changed from pci 9060 to pci 9080 pcicr 04/04 4 memory write and invalidate now supported pcisr 06/06 6 user definable bit added pciclsr 0c/0c 7:0 cache line size is now used for memory write and invalidate pcibar0 10/10 8:6 register bank size changed from 128 to 256 pcibar1 14/14 8:6 register bank size changed from 128 to 256 pcibar3 1c/1c 31:0 base address register for local address space 1 pcisvid 2c/2c 15:0 subsystem vendor id register pcisid 2e/2e 15:0 subsystem id register 31:0 mode/arbitration register now accessible from pci bus 21 local bus direct slave give up bus mode 22 direct slave lock enable 23 pci request mode 24 pci rev 2.1 mode 25 pci read/no write mode 26 pci read with write flush mode 27 get the local bus latency timer with breq marbr 08, ac/88, 12c 28 pci read/no flush mode bigend 0c/8c 7:0 big/little endian descriptor register eromba 14/94 5 breqo timer resolution control 1:0 local bus width now programmable in s mode 10 read prefetch count enable 14:11 read prefetch count 17:16 local bus width now programmable in s mode lbrd0 18/98 25 extra long serial eeprom load bit 12, 3 direct master read prefetch size control 10, 8:5 programmable almost full flag increased by two bits 11 direct master prefetch limit 13 i/o remap select dmpbam 28/a8 15:14 direct master write delay las1rr f0/170 31:0 local address space 1 range register las1ba f4/174 31:0 local address space 1 local base address register (remap) lbrd1 f8/178 31:0 local address space 1 bus region descriptor register mbox0 40, 78/c0 31:0 mbox0 moved to pci address 78 when messaging queue is enabled mbox1 44, 7c/c4 31:0 mbox1 moved to pci address 7c when messaging queue is enabled
section 4 pci 9080 registers ? plx technology, inc., 1997 page 45 version 1.02 table 4-2. register differences between pci 9080 and pci 9060 (continued) register pci/local offset bits description 3 mailbox interrupt enable 28 mailbox 0 interrupt status 29 mailbox 1 interrupt status 30 mailbox 2 interrupt status intcsr 68/e8 31 mailbox 3 interrupt status pcihidr 70/f0 31:0 pci permanent configuration id register pcihrev 74/f4 7:0 pci permanent revision id register 13 write and invalidate mode for dma channel 0 transfers 13 dma write and invalidate mode 14 dma eot[1:0]# (end of transfer) input pin enable 15 dma stop data transfer mode 16 dma clear count mode dmamode0 80/100 17 dma interrupt select dmadpr0 90/110 0 dma descriptor location selector (pci or local) 13 dma write and invalidate mode 14 dma eot[1:0]# (end of transfer) input pin enable 15 dma stop data transfer mode 16 dma clear count mode dmamode1 94/114 17 dma interrupt select dmadpr1 a4/124 0 dma descriptor location selector (pci or local) dmacsr0 a8/128 4 dma channel 0 done dmacsr1 a9/129 4 dma channel 1 done dmathr b0/130 15:0 changed thresholds to accommodate 32 word write fifos opqis 30/b0 31:0 outbound post queue interrupt status register opqim 34/b4 31:0 outbound post queue interrupt mask register iqp 40 31:0 inbound queue port oqp 44 31:0 outbound queue port mqcr c0/140 31:0 messaging queue configuration register qbar c4/144 31:0 queue base address register ifhpr c8/148 31:0 inbound free head pointer register iftpr cc/14c 31:0 inbound free tail pointer register iphpr d0/150 31:0 inbound post head pointer register iptpr d4/154 31:0 inbound post tail pointer register ofhpr d8/158 31:0 outbound free head pointer register oftpr dc/15c 31:0 outbound free tail pointer register ofhpr e0/160 31:0 outbound post head pointer register optpr e4/164 31:0 outbound post tail pointer register qsr e8/168 7:0 queue status/control register
section 4 pci 9080 registers ? plx technology, inc., 1997 page 46 version 1.02 table 4-3. register differences between pci 9080 and pci 9060es register pci/local offset bits description pciidr 00/00 31:16 default changed from pci 906e to pci 9080 pcisr 06/06 6 user definable bit added pciclsr 0c/0c 7:0 cache line size is now used for memory write and invalidate pcibar0 10/10 8:6 register bank size changed from 128 to 256 pcibar1 14/14 8:6 register bank size changed from 128 to 256 pcibar3 1c/1c 31:0 base address register for local address space 1 pcisvid 2c/2c 15:0 subsystem vendor id register pcisid 2e/2e 15:0 subsystem id register 20:19 dma channel priority 23 pci request mode 25 pci read/no write mode 26 pci read with write flush mode 27 get the local bus latency timer with breq marbr 08, ac/88, 12c 28 pci read/no flush mode 5 direct slave big endian mode 6 dma channel 1 big endian mode bigend 0c/8c 7 dma channel 0 big endian mode eromba 14/94 5 breqo timer resolution control 1:0 local bus width now programmable in s mode 15 single read access mode removed 17:16 local bus width now programmable in s mode lbrd0 18/98 25 extra long serial eeprom load bit 12, 3 direct master read prefetch size control 10, 8:5 programmable almost full flag increased by one bit 11 direct master prefetch limit 13 i/o remap select dmpbam 28/a8 15:14 direct master write delay las1rr f0/170 31:0 local address space 1 range register las1ba f4/174 31:0 local address space 1 local base address register (remap) lbrd1 f8/178 31:0 local address space 1 bus region descriptor register mbox0 40, 78/c0 31:0 mbox0 moved to pci address 78 when messaging queue is enabled mbox1 44, 7c/c4 31:0 mbox1 moved to pci address 7c when messaging queue is enabled mbox4 50/d0 31:0 mbox4 added mbox5 54/d4 31:0 mbox5 added mbox6 58/d8 31:0 mbox6 added mbox7 5c/dc 31:0 mbox7 added p2ldbell 60/e0 31:8 24 more doorbell bits added to pci to local doorbell register l2pdbell 64/e4 31:8 24 more doorbell bits added to local to pci doorbell register intcsr 68/e8 3 mailbox interrupt enable
section 4 pci 9080 registers ? plx technology, inc., 1997 page 47 version 1.02 table 4-3. register differences between pci 9080 and pci 9060es (continued) register pci/local offset bits description 18 dma channel 0 interrupt enable 19 dma channel 1 interrupt enable 21 dma channel 0 interrupt status 22 dma channel 1 interrupt status 25 dma channel 0 active during abort 26 dma channel 1 active during abort 28 mailbox 0 interrupt status 29 mailbox 1 interrupt status 30 mailbox 2 interrupt status intcsr 68/e8 31 mailbox 3 interrupt status 3:0 read command for dma cntrl 6c/ec 7:4 write command for dma pcihrev 74/f4 7:0 pci permanent revision id register dmamode0 80/100 31:0 dma channel 0 mode register dmapadr0 84/104 31:0 dma channel 0 pci address register dmaladr0 88/108 31:0 dma channel 0 local address register dmasiz0 8c/10c 31:0 dma channel 0 size register dmadpr0 90/110 31:0 dma channel 0 descriptor pointer register dmamode1 94/114 31:0 dma channel 1 mode register dmapadr1 98/108 31:0 dma channel 1 pci address register dmaladr1 9c/11c 31:0 dma channel 1 local address register dmasiz1 a0/120 31:0 dma channel 1 size register dmadpr1 a4/124 31:0 dma channel 1 descriptor pointer register dmacsr0 a8/128 7:0 dma channel 0 command/status dmacsr1 a9/129 7:0 dma channel 1 command/status dmathr b0/130 31:0 dma threshold register opqis 30/b0 31:0 outbound post queue interrupt status register opqim 34/b4 31:0 outbound post queue interrupt mask register iqp 40 31:0 inbound queue port oqp 44 31:0 outbound queue port mqcr c0/140 31:0 messaging queue configuration register qbar c4/144 31:0 queue base address register ifhpr c8/148 31:0 inbound free head pointer register iftpr cc/14c 31:0 inbound free tail pointer register iphpr d0/150 31:0 inbound post head pointer register iptpr d4/154 31:0 inbound post tail pointer register ofhpr d8/158 31:0 outbound free head pointer register oftpr dc/15c 31:0 outbound free tail pointer register ofhpr e0/160 31:0 outbound post head pointer register optpr e4/164 31:0 outbound post tail pointer register qsr e8/168 7:0 queue status/control register
section 4 pci 9080 registers ? plx technology, inc., 1997 page 48 version 1.02 table 4-4. register differences between pci 9080 and pci 9060sd register pci/local offset bits description pciidr 00/00 31:16 default changed from pci 906d to pci 9080 pcisr 06/06 6 user definable bit added pcibar0 10/10 8:6 register bank size changed from 128 to 256 pcibar1 14/14 8:6 register bank size changed from 128 to 256 pcisvid 2c/2c 15:0 subsystem vendor id register pcisid 2e/2e 15:0 subsystem id register 31:0 mode/arbitration register now accessible from pci bus 23 pci request mode marbr 08, ac/88, 12c 28 pci read/no flush mode 1 direct master big endian mode bigend 0c/8c 7 dma channel 0 big endian mode 3:0 direct slave breqo delay clocks 4 local bus breqo enable eromba 14/94 5 breqo timer resolution control 1:0 local bus width now programmable in s mode 15 single read access mode removed lbrd0 18/98 17:16 local bus width now programmable in s mode dmrr 1c/9c 31:16 local range register for direct master to pci dmlbam 20/a0 31:0 local bus base address register for direct master to pci memory dmlbai 24/a4 31:0 local bus base address register for direct master to pci io/cfg dmpbam 28/a8 31:0 pci base address (remap) register for direct master to pci memory las1rr f0/170 31:0 local address space 1 range register was at 30/b0 in pci 9060sd las1ba f4/174 31:0 local address space 1 local base address register (remap) was at 34/b4 in pci 9060sd lbrd1 f8/178 31:0 local address space 1 bus region descriptor register was at 38/b8 in pci 9060sd lbrd1 f8/178 15 single read access mode removed mbox0 40,78/c0 31:0 mbox0 moved to pci address 78 when messaging queue is enabled mbox1 44, 7c/c4 31:0 mbox1 moved to pci address 7c when messaging queue is enabled mbox4 50/d0 31:0 mbox4 added mbox5 54/d4 31:0 mbox5 added mbox6 58/d8 31:0 mbox6 added mbox7 5c/dc 31:0 mbox7 added 18 dma channel 0 interrupt enable 21 dma channel 0 interrupt active 24 direct master active during abort intcsr 68/e8 25 dma channel 0 active during abort pcihrev 74/f4 7:0 pci permanent revision id register
section 4 pci 9080 registers ? plx technology, inc., 1997 page 49 version 1.02 table 4-4. register differences between pci 9080 and pci 9060sd (continued) register pci/local offset bits description dmamode0 80/100 31:0 dma channel 0 mode register dmapadr0 84/104 31:0 dma channel 0 pci address register dmaladr0 88/108 31:0 dma channel 0 local address register dmasiz0 8c/10c 31:0 dma channel 0 transfer size register dmadpr0 90/110 31:0 dma channel 0 descriptor pointer register dmacsr0 a8/128 7:0 dma channel 0 command/status register dmathr b0/130 15:0 dma channel 0 thresholds opqis 30/b0 31:0 outbound post queue interrupt status register opqim 34/b4 31:0 outbound post queue interrupt mask register iqp 40 31:0 inbound queue port oqp 44 31:0 outbound queue port mqcr c0/140 31:0 messaging queue configuration register qbar c4/144 31:0 queue base address register ifhpr c8/148 31:0 inbound free head pointer register iftpr cc/14c 31:0 inbound free tail pointer register iphpr d0/150 31:0 inbound post head pointer register iptpr d4/154 31:0 inbound post tail pointer register ofhpr d8/158 31:0 outbound free head pointer register oftpr dc/15c 31:0 outbound free tail pointer register ofhpr e0/160 31:0 outbound post head pointer register optpr e4/164 31:0 outbound post tail pointer register qsr e8/168 7:0 queue status/control register
section 4 pci 9080 registers ? plx technology, inc., 1997 page 50 version 1.02 4.2 register address mapping 4.2.1 pci configuration registers table 4-5. pci configuration registers to ensure software compatibility with other versions of the pci 9080 family and to ensure compatibility with future enhancements, write a zero to all unused bits. pci cfg register address local access (offset from chip select address) 31 24 23 16 15 8 70 pci/local writable serial eeprom writable 00h 00h device id vendor id local y 04h 04h status command y n 08h 08h class code revision id local y 0ch 0ch bist header type pci latency timer cache line size y [15:0], local n 10h 10h pci base address 0 for memory mapped configuration registers (pcibar0) y n 14h 14h pci base address 1 for i/o mapped configuration registers (pcibar1) y n 18h 18h pci base address 2 for local address space 0 (pcibar2) y n 1ch 1ch pci base address 3 for local address space 1 (pcibar3) y n 20h 20h unused base address (pcibar4) n n 24h 24h unused base address (pcibar5) n n 28h 28h cardbus cis pointer (not supported) n n 2ch 2ch subsystem id subsystem vendor id local y 30h 30h pci base address for local expansion rom y n 34h 34h reserved n n 38h 38h reserved n n 3ch 3ch max_lat min_gnt interrupt pin interrupt line y [7:0], local y note: refer to the pci 2.1 spec for definitions of these registers.
section 4 pci 9080 registers ? plx technology, inc., 1997 page 51 version 1.02 4.2.2 local configuration registers table 4-6. local configuration registers pci (offset from base address) local access (offset from chip select address) to ensure software compatibility with other versions of the pci 9080 family and to ensure compatibility with future enhancements, write a zero to all unused bits. 31 0 pci/local writable serial eeprom writable 00h 80h range for pci to local address space 0 y y 04h 84h local base address (remap) for pci to local address space 0 y y 08h 88h mode/arbitration register y y 0ch 8ch big/little endian descriptor register y y 10h 90h range for pci to local expansion rom y y 14h 94h local base address (remap) for pci to local expansion rom and breqo control y y 18h 98h local bus region descriptors (space 0 and expansion rom) for pci to local accesses yy 1ch 9ch range for direct master to pci y y 20h a0h local base address for direct master to pci memory y y 24h a4h local base address for direct master to pci io/cfg y y 28h a8h pci base address (remap) for direct master to pci y y 2ch ach pci configuration address register for direct master to pci io/cfg y y f0h 170h range for pci to local address space 1 y y f4h 174h local base address (remap) for pci to local address space 1 y y f8h 178h local bus region descriptor (space 1) for pci to local accesses y y
section 4 pci 9080 registers ? plx technology, inc., 1997 page 52 version 1.02 4.2.3 runtime registers table 4-7. runtime registers pci (offset from base address) local access (offset from chip select address) to ensure software compatibility with other versions of the pci 9080 family and to ensure compatibility with future enhancements, write a zero to all unused bits. 31 0 pci/local writable serial eeprom writable 40h c0h mailbox register 0 1 yy 44h c4h mailbox register 1 1 yy 48h c8h mailbox register 2 y n 4ch cch mailbox register 3 y n 50h d0h mailbox register 4 y n 54h d4h mailbox register 5 y n 58h d8h mailbox register 6 y n 5ch dch mailbox register 7 y n 60h e0h pci to local doorbell register y n 64h e4h local to pci doorbell register y n 68h e8h interrupt control / status y n 6ch ech serial eeprom control, pci command codes, user i/o control, init control y n 70h f0h device id vendor id n n 74h f4h unused revision id n n 78h c0h mailbox register 0 1 yn 7ch c4h mailbox register 1 1 yn note: mailbox registers 0 and 1 are always accessible at addresses 78h/c0h and 7ch/c4. when the i 2 o feature is disabled (bit 0 of qsr register = 0), mailbox registers 0 and 1 are also accessible at pci addresses 40h and 44h for pci 9060 compatibility. when the i 2 o feature is enabled, the inbound and outbound queue pointers are accessed at addresses 40h and 44h, replacing the mailbox registers in the pci address space.
section 4 pci 9080 registers ? plx technology, inc., 1997 page 53 version 1.02 4.2.4 dma registers table 4-8. dma registers pci (offset from base address) local access (offset from chip select address) to ensure software compatibility with other versions of the pci 9080 family and to ensure compatibility with future enhancements, write a zero to all unused bits. 31 0 pci/local writable serial eeprom writable 80h 100h dma ch 0 mode y n 84h 104h dma ch 0 pci address y n 88h 108h dma ch 0 local address y n 8ch 10ch dma ch 0 transfer byte count y n 90h 110h dma ch 0 descriptor pointer y n 94h 114h dma ch 1 mode y n 98h 118h dma ch 1 pci address y n 9ch 11ch dma ch 1 local address y n a0h 120h dma ch 1 transfer byte count y n a4h 124h dma ch 1 descriptor pointer y n a8h 128h reserved dma channel 1 command/status register dma channel 0 command/status register yn ach 12ch mode/arbitration register y n b0h 130h dma threshold register y n
section 4 pci 9080 registers ? plx technology, inc., 1997 page 54 version 1.02 4.2.5 messaging queue registers table 4-9. messaging queue registers pci (offset from base address) local access (offset from chip select address) to ensure software compatibility with other versions of the pci 9080 family and to ensure compatibility with future enhancements, write a zero to all unused bits. 31 0 pci/local writable serial eeprom writable 30h b0h outbound post queue interrupt status n n 34h b4h outbound post queue interrupt mask y n 40h inbound queue port pci n 44h outbound queue port pci n c0h 140h messaging unit configuration register y n c4h 144h queue base address register y n c8h 148h inbound free head pointer register y n cch 14ch inbound free tail pointer register y n d0h 150h inbound post head pointer register y n d4h 154h inbound post tail pointer register y n d8h 158h outbound free head pointer register y n dch 15ch outbound free tail pointer register y n e0h 160h outbound post head pointer register y n e4h 164h outbound post tail pointer register y n e8h 168h queue status/control register y n notes: when i 2 o messaging is enabled (bit 0 of qsr register = 1), a pci master (host or another iop) uses the inbound queue port to read mfas from the inbound free list fifo and to write mfas to the inbound post list fifo. it uses the outbound queue port to read mfas from the outbound post list fifo and to write mfas to the outbound free list fifo. each inbound message frame address (mfa) is specified by i 2 o as the offset from the pci base address 0 (programmed in register pcibar0 at offset 10h) to the start of the message frame. this means that all inbound message frames should reside in pci base address 0 memory space. each outbound message frame address (mfa) is specified by i 2 o as the offset from system address 0x00000000h. so the outbound mfa is the physical 32-bit address of the frame in shared pci system memory. inbound and outbound queues may reside in local address space 0 or 1 by programming the qsr register. they need not be in shared memory.
section 4 pci 9080 registers ? plx technology, inc., 1997 page 55 version 1.02 4.3 pci configuration registers all registers may be written to or read from in byte, word, or lword accesses. 4.3.1 (pciidr; pci:00h, loc:00h) pci configuration id register table 4-10. (pciidr; pci:00h, loc:00h) pci configuration id register field description read write value after reset 15:0 vendor id. identifies device manufacturer. defaults to the pci sig issued vendor id of plx (10b5h) if no serial eeprom is present and pin nb# (no local bus initialization) is asserted low. yes local/ serial eeprom 10b5h or 0 31:16 device id. identifies the particular device. defaults to the plx part number for pci interface chip (pci 9080) if no serial eeprom is present and pin nb# (no local bus initialization) is asserted low. yes local/ serial eeprom 9080h or 0 4.3.2 (pcicr; pci:04h, loc:04h) pci command register table 4-11. (pcicr; pci:04h, loc:04h) pci command register field description read write value after reset 0 i/o space. value of 1 allows device to respond to i/o space accesses. value of 0 disables device from responding to i/o space accesses. yes yes 0 1 memory space. value of 1 allows device to respond to memory space accesses. value of 0 disables device from responding to memory space accesses. yes yes 0 2 master enable. value of 1 allows device to behave as a bus master. value of 0 disables device from generating bus master accesses. this bit must be set for the pci 9080 to perform direct master or dma cycles. yes yes 0 3 special cycle. (this bit is not supported.) yes no 0 4 memory write/invalidate enable bit. value of 1 enables memory write/invalidate. value of 0 disables memory write/invalidate. (refer to the dma mode registers (dm, dmamode0, and dmamode1) bit 13.) (refer to table 4-43[13], table 4-62[13], and table 4-67[13], respectively.) yes yes 0 5 vga palette snoop. (this bit is not supported.) yes no 0 6 parity error response. value of 0 indicates a parity error is ignored and operation continues. value of 1 indicates parity checking is enabled. yes yes 0 7 wait cycle control. controls whether the device performs address/data stepping. value of 0 indicates device never does stepping. value of 1 indicates device always does stepping. note: hardcoded to 0. yes no 0 8 serr# enable. value of 1 enables serr# driver. value of 0 disables serr# driver. yes yes 0 9 fast back-to-back enable. indicates type of fast back-to-back transfers master can perform on bus. value of 1 indicates fast back-to-back transfers can occur to any agent on bus. value of 0 indicates fast back-to-back transfers can only occur to same agent as previous cycle. yes no 0 15:10 reserved. yes no 0
section 4 pci 9080 registers ? plx technology, inc., 1997 page 56 version 1.02 4.3.3 (pcisr; pci:06h, loc:06h) pci status register table 4-12. (pcisr; pci:06h, loc:06h) pci status register field description read write value after reset 5:0 reserved. yes no 0 6 if high, supports user definable features. this bit can only be written from the local side. it is read-only from the pci side. yes local 0 7 fast back-to-back capable. when this bit is set to 1, it indicates the adapter can accept fast back-to-back transactions. value of 0 indicates adapter cannot. yes no 1 8 master data parity error detected. this bit is set to 1 when three conditions are met: 1) the pci 9080 asserted perr# itself or observed perr# asserted; 2) the pci 9080 was the bus master for the operation in which the error occurred; 3) the parity error response bit in the command register is set. writing 1 to this bit clears the bit (0). yes yes/clr 0 10:9 devsel timing. indicates timing for devsel# assertion. value of 01 indicates a medium decode. note: hardcoded to 01. yes no 01 11 target abort. when this bit is set to 1, this bit indicates the pci 9080 has signaled a target abort. writing 1 to this bit clears the bit (0). yes yes/clr 0 12 received target abort. when set to 1, this bit indicates the pci 9080 has received a target abort signal. writing 1 to this bit clears the bit (0). yes yes/clr 0 13 master abort. when set to 1, this bit indicates the pci 9080 has generated a master abort signal. writing 1 to this bit clears the bit (0). yes yes/clr 0 14 signaled system error. when set to 1, this bit indicates the pci 9080 has reported a system error on the serr# signal. writing 1 to this bit clears the bit (0). yes yes/clr 0 15 detected parity error. when set to 1, this bit indicates the pci 9080 has detected a pci bus parity error, even if parity error handling is disabled (the parity error response bit in the command register is clear). one of three conditions can cause this bit to be set. 1) the pci 9080 detected a parity error during a pci address phase; 2) the pci 9080 detected a data parity error when it was the target of a write; 3) the pci 9080 detected a data parity error when performing a master read operation. writing 1 to this bit clears the bit (0). yes yes/clr 0 4.3.4 (pcirev; pci:08h, loc:08h) pci revision id register table 4-13. (pcirev; pci:08h, loc:08h) pci revision id register field description read write value after reset 7:0 revision id. silicon revision of pci 9080. yes local/ serial eeprom current rev #
section 4 pci 9080 registers ? plx technology, inc., 1997 page 57 version 1.02 4.3.5 (pciccr; pci:09-0bh, loc:09-0bh) pci class code register table 4-14. (pciccr; pci:09-0bh, loc:09-0bh) pci class code register field description read write value after reset 7:0 register level programming interface. 00h = queue ports at 40h and 44h. 01h = queue ports at 40h and 44h, and int status and int mask at 30h and 34h, respectively. yes local/ serial eeprom 00 15:8 subclass code. 80h = other bridge device, 00h = i 2 o device. yes local/ serial eeprom 80h 23:16 base class code. 06h = bridge device, 0eh = i 2 o controller. yes local/ serial eeprom 06h 4.3.6 (pciclsr; pci:0ch, loc:0ch) pci cache line size register table 4-15. (pciclsr; pci:0ch, loc:0ch) pci cache line size register field description read write value after reset 7:0 system cache line size in units of 32-bit words. yes yes 0 4.3.7 (pciltr; pci:0dh, loc:0dh) pci latency timer register table 4-16. (pciltr; pci:0dh, loc:0dh) pci latency timer register field description read write value after reset 7:0 pci latency timer. units of pci bus clocks that specify the amount of time the pci 9080, as a bus master, can burst data on the pci bus. yes yes 0 4.3.8 (pcihtr; pci:0eh, loc:0eh) pci header type register table 4-17. (pcihtr; pci:0eh, loc:0eh) pci header type register field description read write value after reset 6:0 configuration layout type. specifies the layout of bits 10h through 3fh in configuration space. only one encoding 0 is defined. all other encodings are reserved. yes local 0 7 header type. value of 1 indicates multiple functions. value of 0 indicates a single function. yes local 0
section 4 pci 9080 registers ? plx technology, inc., 1997 page 58 version 1.02 4.3.9 (pcibistr; pci:0fh, loc:0fh) pci built-in self test (bist) register table 4-18. (pcibistr; pci:0fh, loc:0fh) pci built-in self test (bist) register field description read write value after reset 3:0 value of 0 indicates device passed its test. nonzero values indicate the device failed. device specific failure codes can be encoded in the nonzero value. yes local 0 5:4 reserved. device returns 0. yes no 0 6 pci writes a 1 to invoke bist. generates an interrupt to local bus. local bus resets the bit when bist is complete. software should fail device if bist is not complete after two seconds. refer to runtime registers for interrupt control/status. yes yes 0 7 returns 1 if the device supports bist. returns 0 if the device is not bist compatible. yes local 0 4.3.10 (pcibar0; pci:10h, loc:10h) pci base address register for memory accesses to local, runtime, and dma registers table 4-19. (pcibar0; pci:10h, loc:10h) pci base address register for memory accesses to local, runtime, and dma registers field description read write value after reset 0 memory space indicator. value of 0 indicates register maps into memory space. value of 1 indicates register maps into i/o space. note: hardcoded to 0. yes no 0 2:1 location of register. location values: 00locate anywhere in 32 bit memory address space 01locate below 1 mb memory address space 10locate anywhere in 64 bit memory address space 11reserved note: hardcoded to 0. yes no 0 3 prefetchable. value of 1 indicates there are no side effects on reads. this bit has no effect on the operation of the pci 9080. note: hardcoded to 0. yes no 0 7:4 memory base address. memory base address for access to local, runtime, and dma registers (default is 256 bytes). note: hardcoded to 0. yes no 0 31:8 memory base address. memory base address for access to local, runtime, and dma registers. yes yes 0 note: for i 2 o, the inbound message frame pool must reside in the address space pointed to by pcibar0. message frame address (mfa) is defined by i 2 o as the offset from this base address to the start of the message frame.
section 4 pci 9080 registers ? plx technology, inc., 1997 page 59 version 1.02 4.3.11 (pcibar1; pci:14h, loc:14h) pci base address register for i/o accesses to local, runtime, and dma registers table 4-20. (pcibar1; pci:14h, loc:14h) pci base address register for i/o accesses to local, runtime, and dma registers field description read write value after reset 0 memory space indicator. value of 0 indicates register maps into memory space. value of 1 indicates register maps into i/o space. note: hardcoded to 1. yes no 1 1 reserved. yes no 0 7:2 i/o base address. base address for i/o access to local, runtime, and dma registers. (default is 256 bytes) note: hardcoded to 0. yes no 0 31:8 i/o base address. base address for i/o access to local, runtime, and dma registers. yes yes 0 4.3.12 (pcibar2; pci:18h, loc:18h) pci base address register for memory accesses to local address space 0 table 4-21. (pcibar2; pci:18h, loc:18h) pci base address register for memory accesses to local address space 0 field description read write value after reset 0 memory space indicator. value of 0 indicates register maps into memory space. value of 1 indicates register maps into i/o space. (specified in las0rr register.) yes no 0 2:1 location of register (if memory space). location values: 00locate anywhere in 32 bit memory address space 01locate below 1 mb memory address space 10locate anywhere in 64 bit memory address space 11reserved (specified in las0rr register.) if i/o space, bit 1 is always 0 and bit 2 is included in the base address. yes mem: no i/o: bit 1 no, bit 2 yes 0 3 prefetchable (if memory space). value of 1 indicates there are no side effects on reads. this bit reflects the value of bit 3 in the las0rr register and provides only status to the system. this bit has no effect on the operation of the pci 9080. prefetching features of this address space are controlled by the associated bus region descriptor register. (specified in las0rr register.) if i/o space, bit 3 is included in the base address. yes mem: no i/o: yes 0 31:4 memory base address. memory base address for access to local address space 0. yes yes 0 note: pcibar2 can be enabled or disabled by setting or clearing bit 0 in the las0ba register.
section 4 pci 9080 registers ? plx technology, inc., 1997 page 60 version 1.02 4.3.13 (pcibar3; pci:1ch, loc:1ch) pci base address register for memory accesses to local address space 1 table 4-22. (pcibar3; pci:1ch, loc:1ch) pci base address register for memory accesses to local address space 1 field description read write value after reset 0 memory space indicator. value of 0 indicates register maps into memory space. value of 1 indicates register maps into i/o space. (specified in las1rr register.) yes no 0 2:1 location of register. location values: 00locate anywhere in 32 bit memory address space 01locate below 1 mb memory address space 10locate anywhere in 64 bit memory address space 11reserved (specified in las1rr register.) if i/o space, bit 1 is always 0 and bit 2 is included in the base address. yes mem: no i/o: bit 1 no, bit 2 yes 0 3 prefetchable (if memory space). value of 1 indicates there are no side effects on reads. this bit reflects the value of bit 3 in the las1rr register and only provides status to the system. this bit has no effect on the operation of the pci 9080. prefetching features of this address space are controlled by the associated bus region descriptor register. (specified in las1rr register.) if i/o space, bit 3 is included in the base address. yes mem: no i/o: yes 0 31:4 memory base address. memory base address for access to local address space 1. yes yes 0 note: pcibar3 can be enabled or disabled by setting or clearing bit 0 in the las1ba register. if qsr bit 0 is set, pcibar3 returns 0. 4.3.14 (pcibar4; pci:20h, loc:20h) pci base address register table 4-23. (pcibar4; pci:20h, loc:20h) pci base address register field description read write value after reset 31:0 reserved. yes no 0 4.3.15 (pcibar5; pci:24h, loc:24h) pci base address register table 4-24. (pcibar5; pci:24h, loc:24h) pci base address register field description read write value after reset 31:0 reserved. yes no 0
section 4 pci 9080 registers ? plx technology, inc., 1997 page 61 version 1.02 4.3.16 (pcicis; pci:28h, loc:28h) pci cardbus cis pointer register table 4-25. (pcicis; pci:28h, loc:28h) pci cardbus cis pointer register field description read write value after reset 31:0 cardbus information structure pointer for pcmcia. (not supported.) yes no 0 4.3.17 (pcisvid; pci:2ch, loc:2ch) pci subsystem vendor id register table 4-26. (pcisvid; pci:2ch, loc:2ch) pci subsystem vendor id register field description read write value after reset 15:0 subsystem vendor id (unique add-in board vendor id). yes local/ serial eeprom 10b5 4.3.18 (pcisid; pci:2eh, loc:2eh) pci subsystem id register table 4-27. (pcisid; pci:2eh, loc:2eh) pci subsystem id register field description read write value after reset 15:0 subsystem id (unique add-in board device id). yes local/ serial eeprom 9080h 4.3.19 (pcierbar; pci:30h, loc:30h) pci expansion rom base register table 4-28. (pcierbar; pci:30h, loc:30h) pci expansion rom base register field description read write value after reset 0 address decode enable. value of 1 indicates device accepts accesses to the expansion rom address. value of 0 indicates device does not accept accesses to expansion rom space. should be set to 1 by pci host if expansion rom is present. yes yes 0 10:1 reserved. yes no 0 31:11 expansion rom base address (upper 21 bits). yes yes 0 4.3.20 (pciilr; pci:3ch, loc:3ch) pci interrupt line register table 4-29. (pciilr; pci:3ch, loc:3ch) pci interrupt line register field description read write value after reset 7:0 interrupt line routing value. indicates which input of the system interrupt controller(s) to which the interrupt line of the device is connected. yes yes 0
section 4 pci 9080 registers ? plx technology, inc., 1997 page 62 version 1.02 4.3.21 (pciipr; pci:3dh, loc:3dh) pci interrupt pin register table 4-30. (pciipr; pci:3dh, loc:3dh) pci interrupt pin register field description read write value after reset 7:0 interrupt pin register. indicates which interrupt pin the device uses. the following values are decoded: 0 = no interrupt pin 1 = inta# 2 = intb# 3 = intc# 4 = intd# note: pci 9080 supports only one pci interrupt pin (inta#). yes local/ serial eeprom 1 4.3.22 (pcimgr; pci:3eh, loc:3eh) pci min_gnt register table 4-31. (pcimgr; pci:3eh, loc:3eh) pci min_gnt register field description read write value after reset 7:0 min_gnt. specifies how long a burst period the device needs, assuming a clock rate of 33 mhz. value is multiple of 1/4 sec increments. yes local/ serial eeprom 0 4.3.23 (pcimlr; pci:3fh, loc:3fh) pci max_lat register table 4-32. (pcimlr; pci:3fh, loc:3fh) pci max_lat register field description read write value after reset 7:0 max_lat. specifies how often the device must gain access to the pci bus. value is multiple of 1/4 sec increments. yes local/ serial eeprom 0
section 4 pci 9080 registers ? plx technology, inc., 1997 page 63 version 1.02 4.4 local configuration registers 4.4.1 (las0rr; pci:00h, loc:80h) local address space 0 range register for pci to local bus table 4-33. (las0rr; pci:00h, loc:80h) local address space 0 range register for pci to local bus field description read write value after reset 0 memory space indicator. value of 0 indicates local address space 0 maps into pci memory space. value of 1 indicates address space 0 maps into pci i/o space. yes yes 0 2:1 if mapped into memory space, encoding is as follows: 2/1 meaning 0 0 locate anywhere in 32 bit pci address space 0 1 locate below 1 mb in pci address space 1 0 locate anywhere in 64 bit pci address space 1 1 reserved if mapped into i/o space, bit 1 must be set to 0. bit 2 is included with bits [31:3] to indicate decoding range. yes yes 0 3 if mapped into memory space, a value of 1 indicates reads are prefetchable (bit has no effect on the operation of the pci 9080, but is used for system status). if mapped into i/o space, bit is included with bits [31:2] to indicate decoding range. yes yes 0 31:4 specifies which pci address bits to use for decoding a pci access to local bus space 0. each bit corresponds to a pci address bit. bit 31 corresponds to address bit 31. write a value of 1 to all bits to be included in decode and a 0 to all others (used in conjunction with pci configuration register 18h). default is 1 mb. yes yes fff0000h notes: range ( not range register) must be power of 2. range register value is the inverse of range. user should limit all i/o spaces to 256 bytes per pci v2.1 spec. 4.4.2 (las0ba; pci:04h, loc:84h) local address space 0 local base address (remap) register table 4-34. (las0ba; pci:04h, loc:84h) local address space 0 local base address (remap) register field description read write value after reset 0 space 0 enable. value of 1 enables decoding of pci addresses for direct slave access to local space 0. value of 0 disables decoding. if this bit is set to 0, the pci bios may not allocate (assign) the base address for space 0. note: must be set to 1 for any direct slave access to space 0 . yes yes 0 1 reserved. yes no 0 3:2 if local space 0 is mapped into memory space, bits are not used. if mapped into i/o space, bit is included with bits [31:4] for remapping. yes yes 0 31:4 remap of pci address to local address space 0 into a local address space. the bits in this register remap (replace) the pci address bits used in decode as the local address bits. note: remap address value must be multiple of range ( not the range register). yes yes 0
section 4 pci 9080 registers ? plx technology, inc., 1997 page 64 version 1.02 4.4.3 (marbr; pci:08h or ach, loc:88h or 12ch) mode/arbitration register table 4-35. (marbr; pci:08h or ach, loc:88h or 12ch) mode/arbitration register field description read write value after reset 7:0 local bus latency timer. number of local bus clock cycles before negating hold and releasing the local bus. this timer is also used with bit 27 to delay breq input to give up the local bus only when this timer expires. yes yes 00 15:8 local bus pause timer. number of local bus clock cycles before reasserting hold after releasing the local bus. note: applicable only to dma operation. yes yes 00 16 local bus latency timer enable. value of 1 enables latency timer. yes yes 0 17 local bus pause timer enable. value of 1 enables pause timer. yes yes 0 18 local bus breq enable. value of 1 enables local bus breq input. when the breq input is active, pci 9080 negates hold and releases the local bus. yes yes 0 20:19 dma channel priority. value of 00 indicates a rotational priority scheme. value of 01 indicates channel 0 has priority. value of 10 indicates channel 1 has priority. value of 11 is reserved. yes yes 0 21 local bus direct slave give up bus mode. when set to 1, pci 9080 negates hold and releases the local bus when the direct slave write fifo becomes empty during a direct slave write or when the direct slave read fifo becomes full during a direct slave read. yes yes 1 22 direct slave llocko# enable. value of 1 enables pci direct slave locked sequences. value of 0 disables direct slave locked sequences. yes yes 0 23 pci request mode. value of 1 causes pci 9080 to negate req when it asserts frame during a master cycle. value of 0 causes pci 9080 to leave req asserted for the entire bus master cycle. yes yes 0 24 pci rev 2.1 mode. when set to 1, pci 9080 operates in delayed transaction mode for direct slave reads. pci 9080 issues a retry and prefetches the read data. yes yes 0 25 pci read no write mode. value of 1 forces a retry on writes if read is pending. value of 0 allows writes to occur while read is pending. yes yes 0 26 pci read with write flush mode. value of 1 submits a request to flush a pending read cycle if a write cycle is detected. value of 0 submits a request to not effect pending reads when a write cycle occurs (pci v2.1 compatible). yes yes 0 27 gate the local bus latency timer with breq. if this bit is set to 0, pci 9080 gives up the local bus during direct slave or dma transfer after the current cycle (if enabled and breq is sampled). if this bit is set to 1, pci 9080 gives up the local bus only (if breq is sampled) and the local bus latency timer is enabled and expired during direct slave or dma transfer. yes yes 0 28 pci read no flush mode. value of 1 submits request to not flush the read fifo if pci read cycle completes (read ahead mode). value of 0 submits request to flush read fifo if pci read cycle completes. yes yes 0 29 if set to 0, reads from the pci configuration register address 00h and returns the device id and vendor id. if set to 1, reads from the pci configuration register address 00h and returns the subsystem id and subsystem vendor id. yes yes 0 31:30 reserved. yes no 0
section 4 pci 9080 registers ? plx technology, inc., 1997 page 65 version 1.02 4.4.4 (bigend; pci:0ch, loc:8ch) big/little endian descriptor register table 4-36. (bigend; pci:0ch, loc:8ch) big/little endian descriptor register field description read write value after reset 0 configuration register big endian mode. value of 1 specifies use of big endian data ordering for local accesses to the configuration registers. value of 0 specifies little endian ordering. big endian mode can be specified for configuration register accesses by asserting the bigend# pin during the address phase of the access. yes yes 0 1 direct master big endian mode. value of 1 specifies use of big endian data ordering for direct master accesses. value of 0 specifies little endian ordering. big endian mode can be specified for direct master accesses by asserting the bigend# input pin during the address phase of the access. yes yes 0 2 direct slave address space 0 big endian mode. value of 1 specifies use of big endian data ordering for direct slave accesses to local address space 0. value of 0 specifies little endian ordering. yes yes 0 3 direct slave address expansion rom 0 big endian mode. value of 1 specifies use of big endian data ordering for direct slave accesses to expansion rom. value of 0 specifies little endian ordering. yes yes 0 4 big endian byte lane mode. value of 1 specifies that in big endian mode, use byte lanes 31:16 for a 16 bit local bus and byte lanes 31:24 for an 8 bit local bus. value of 0 specifies that in big endian mode, byte lanes 15:0 be used for a 16 bit local bus and byte lanes 7:0 for an 8 bit local bus. yes yes 0 5 direct slave address space 1 big endian mode. value of 1 specifies use of big endian data ordering for direct slave accesses to local address space 1. value of 0 specifies little endian ordering. yes yes 0 6 dma channel 1 big endian mode. value of 1 specifies use of big endian data ordering for dma channel 1 accesses to the local address space. value of 0 specifies little endian ordering. yes yes 0 7 dma channel 0 big endian mode. value of 1 specifies use of big endian data ordering for dma channel 0 accesses to the local address space. value of 0 specifies little endian ordering. yes yes 0 31:8 reserved. yes no 0
section 4 pci 9080 registers ? plx technology, inc., 1997 page 66 version 1.02 4.4.5 (eromrr; pci:10h, loc:90h) expansion rom range register table 4-37. (eromrr; pci:10h, loc:90h) expansion rom range register field description read write value after reset 10:0 reserved. yes no 0 31:11 specifies which pci address bits to use for decoding a pci to local bus expansion rom. each of the bits corresponds to a pci address bit. bit 31 corresponds to address bit 31. write a value of 1 to all bits to be included in decode and a 0 to all others (used in conjunction with pci configuration register 30h). default is 64 kb. yes yes ffff00h note: range ( not range register) must be power of 2. range register value is the inverse of range. 4.4.6 (eromba; pci:14h, loc:94h) expansion rom local base address (remap) register and breqo control table 4-38. (eromba; pci:14h, loc:94h) expansion rom local base address (remap) register and breqo control field description read write value after reset 3:0 direct slave breqo (backoff request out) delay clocks. number of local bus clocks in which a direct slave hold request is pending and a local direct master access is in progress and not being granted the bus (lholda) before asserting breqo. once asserted, breqo remains asserted until the pci 9080 receives lholda (lsb = 8 or 64 clocks). yes yes 0 4 local bus breqo enable. value of 1 enables pci 9080 to assert the breqo output. yes yes 0 5 breqo timer-resolution. value of 1 changes the lsb of the breqo timer from 8 to 64 clocks. yes yes 0 10:6 reserved. yes no 0 31:11 remap of pci expansion rom space into a local address space. the bits in this register remap (replace) the pci address bits used in decode as the local address bits. yes yes 0 note: remap address value must be multiple of range ( not the range register).
section 4 pci 9080 registers ? plx technology, inc., 1997 page 67 version 1.02 4.4.7 (lbrd0; pci:18h, loc:98h) local address space 0/expansion rom bus region descriptor register table 4-39. (lbrd0; pci:18h, loc:98h) local address space 0/expansion rom bus region descriptor register field description read write value after reset 1:0 memory space 0 local bus width. value of 00 indicates bus width of 8 bits, a value of 01 indicates bus width of 16 bits and a value of 10 or 11 indicates bus width of 32 bits. yes yes s = 01 j = 11 c = 11 5:2 memory space 0 internal wait states (data to data; 0-15 wait states). yes yes 0 6 memory space 0 ready input enable. value of 1 enables ready input. value of 0 disables ready input. yes yes 0 7 memory space 0 bterm# input enable. value of 1 enables bterm# input. value of 0 disables bterm# input. if this bit is set to 0, pci 9080 bursts four lword maximum at a time. yes yes 0 8 memory space 0 prefetch disable. if mapped into memory space, a value of 0 enables read prefetching. value of 1 disables prefetching. if prefetching is disabled, pci 9080 disconnects after each memory read. yes yes 0 9 expansion rom space prefetch disable. value of 0 enables read prefetching. value of 1 disables prefetching. if prefetching is disabled, pci 9080 disconnects after each memory read. yes yes 0 10 read prefetch count enable. when set to 1 and memory prefetching is enabled, pci 9080 prefetches up to the number of lwords specified in the prefetch count. when set to 0, pci 9080 ignores the count and continues prefetching until terminated by the pci bus. yes yes 0 14:11 prefetch counter. number of lwords to prefetch during memory read cycles (0-15). a count of zero selects a prefetch of 16 lwords. yes yes 0 15 reserved. yes no 0 17:16 expansion rom space local bus width. value of 00 indicates bus width of 8 bits, a value of 01 indicates bus width of 16 bits and a value of 10 or 11 indicates bus width of 32 bits. yes yes s = 01 j = 11 c = 11 21:18 expansion rom space internal wait states (data to data; 0-15 wait states). yes yes 0 22 expansion rom space ready input enable. value of 1 enables ready input. value of 0 disables ready input. yes yes 0 23 expansion rom space bterm# input enable. value of 1 enables bterm# input. value of 0 disables bterm# input. if this bit is set to 1, pci 9080 bursts four lword maximum at a time. yes yes 0 24 memory space 0 burst enable. value of 1 enables bursting. value of 0 disables bursting. if burst is disabled, the local bus performs continuous single cycles for burst pci read/write cycles. yes yes 0 25 extra long load from serial eeprom. value of 1 loads the subsystem id and local address space 1 registers. value of 0 indicates not to load them. yes no 0 26 expansion rom space burst enable. value of 1 enables bursting. value of 0 disables bursting. if burst is disabled, the local bus performs continuous single cycles for burst pci read/write cycles. yes yes 0 27 direct slave pci write mode. value of 0 indicates pci 9080 should disconnect when the direct slave write fifo is full. value of 1 indicates pci 9080 should de- assert trdy# when the write fifo is full. yes yes 0 31:28 pci target retry delay clocks. contains the value (multiplied by 8) of the number of pci bus clocks after receiving a pci local read or write access and not successfully completing a transfer. only pertains to direct slave writes when bit 27 is set to 1. yes yes 4 (32 clocks)
section 4 pci 9080 registers ? plx technology, inc., 1997 page 68 version 1.02 4.4.8 (dmrr; pci:1ch, loc:9ch) local range register for direct master to pci table 4-40. (dmrr; pci:1ch, loc:9ch) local range register for direct master to pci field description read write value after reset 15:0 reserved (64 kb increments). yes no 0 31:16 specifies which local address bits to use for decoding a local to pci bus access. each of the bits corresponds to a pci address bit. bit 31 corresponds to address bit 31. write a value of 1 to all bits that must be included in decode and a 0 to all others. this range register is used for direct master memory, i/o, or configuration accesses. yes yes 0 note: range ( not range register) must be power of 2. range register value is the inverse of range. 4.4.9 (dmlbam; pci:20h, loc:a0h) local bus base address register for direct master to pci memory table 4-41. (dmlbam; pci:20h, loc:a0h) local bus base address register for direct master to pci memory field description read write value after reset 15:0 reserved. yes no 0 31:16 assigns a value to the bits to use for decoding a local to pci memory access. yes yes 0 note: local base address value must be multiple of range ( not the range register). 4.4.10 (dmlbai; pci:24h, loc:a4h) local base address register for direct master to pci io/cfg table 4-42. (dmlbai; pci:24h, loc:a4h) local base address register for direct master to pci io/cfg field description read write value after reset 15:0 reserved. yes no 0 31:16 assigns a value to the bits to use for decoding a local to pci i/o or configuration access. this base address is used for direct master i/o and configuration accesses. yes yes 0 notes: local base address value must be multiple of range ( not the range register). refer to bit 13 of (loc:a8h) for i/o remap address option (refer to table 4-43).
section 4 pci 9080 registers ? plx technology, inc., 1997 page 69 version 1.02 4.4.11 (dmpbam; pci:28h, loc:a8h) pci base address (remap) register for direct master to pci memory table 4-43. (dmpbam; pci:28h, loc:a8h) pci base address (remap) register for direct master to pci memory field description read write value after reset 0 direct master memory access enable. value of 1 enables decode of direct master memory accesses. value of 0 disables decode of direct master memory accesses. yes yes 0 1 direct master i/o access enable. value of 1 enables decode of direct master i/o accesses. value of 0 disables decode of direct master i/o accesses. yes yes 0 2 llock# input enable. value of 1 enables llock# input, enabling pci-locked sequences. value of 0 disables llock# input. yes yes 0 12, 3 direct master read prefetch size control. values: 00 = pci 9080 continues to prefetch read data from the pci bus until direct master access is finished. this may result in an additional four unneeded lwords being prefetched from the pci bus. 01 = prefetch up to four lwords from the pci bus 10 = prefetch up to eight lwords from the pci bus 11 = prefetch up to 16 lwords from the pci bus if pci memory prefetch is not wanted, performs a direct master single cycle. the direct master burst reads must not exceed the programmed limit. yes yes 00 4 direct master pci read mode. value of 0 indicates pci 9080 should release the pci bus when the read fifo becomes full. value of 1 indicates pci 9080 should keep the pci bus and de-assert irdy when the read fifo becomes full. yes yes 0 10, 8:5 programmable almost full flag. when the number of entries in the 32 word direct master write fifo exceeds this value, the output pin dmpaf# is asserted low. yes yes 000 9 write and invalidate mode. when set to 1, pci 9080 waits for 8 or 16 lwords to be written from the local bus before starting pci access. when set, all local direct master to pci write accesses must be 8 or 16 lword bursts. use in conjunction with (pci:04h)(loc:04h) (refer to table 4-11[4] and section 3.6.1.9.2, direct master write and invalidate). yes yes 0 11 direct master prefetch limit. if set to 1, dont prefetch past 4k (4098 bytes) boundaries. yes yes 0 13 i/o remap select. when set to 1, forces pci address bits [31:16] to all zeros. when set to 0, uses bits [31:16] of this register as pci address bits [31:16]. yes yes 0 15:14 direct master write delay. this register is used to delay the pci bus request after direct master burst write cycle has started. values: 00 = no delay; start the cycle immediately 01 = delay 4 pci clocks 10 = delay 8 pci clocks 11 = delay 16 pci clocks yes yes 00 31:16 remap of local to pci space into a pci address space. the bits in this register remap (replace) the local address bits used in decode as the pci address bits. this pci remap address is used for direct master memory and i/o accesses. yes yes 0 note: remap address value must be multiple of range ( not the range register).
section 4 pci 9080 registers ? plx technology, inc., 1997 page 70 version 1.02 4.4.12 (dmcfga; pci:2ch, loc:ach) pci configuration address register for direct master to pci io/cfg table 4-44. (dmcfga; pci:2ch, loc:ach) pci configuration address register for direct master to pci io/cfg field description read write value after reset 1:0 configuration type (00=type 0, 01=type 1). yes yes 0 7:2 register number. if different register read/write is needed, this register value must be programmed and a new pci configuration cycle must be generated. yes yes 0 10:8 function number. yes yes 0 15:11 device number. yes yes 0 23:16 bus number. yes yes 0 30:24 reserved. yes no 0 31 configuration enable. value of 1 allows local to pci i/o accesses to be converted to a pci configuration cycle. the parameters in this table are used to generate the pci configuration address. yes yes 0 note: refer to the configuration cycle generation example in section 3.6.1.6, cfg (pci configuration type 0 or type 1 cycles). 4.4.13 (las1rr; pci:f0h, loc:170h) local address space 1 range register for pci to local bus table 4-45. (las1rr; pci:f0h, loc:170h) local address space 1 range register for pci to local bus field description read write value after reset 0 memory space indicator. value of 0 indicates local address space 1 maps into pci memory space. value of 1 indicates address space 1 maps into pci i/o space. yes yes 0 2:1 if mapped into memory space, encoding is as follows: 2/1 meaning 0 0 locate anywhere in 32 bit pci address space 0 1 locate below 1 mb in pci address space 1 0 locate anywhere in 64 bit pci address space 1 1 reserved if mapped into i/o space, bit 1 must be set to 0. bit 2 is included with bits [31:3] to indicate decoding range. yes yes 0 3 if mapped into memory space, a value of 1 indicates reads are prefetchable (bit has no effect on the operation of the pci 9080, but is for system status). if mapped into i/o space, bit is included with bits [31:2] to indicate decoding range. yes yes 0 31:4 specifies which pci address bits to use for decoding a pci access to local bus space 1. each of the bits corresponds to a pci address bit. bit 31 corresponds to address bit 31. write a value of 1 to all bits that must be included in decode and a 0 to all others (used in conjunction with pci configuration register ch 1). default is 1 mb. yes yes fff0000h note: range ( not range register) must be power of 2. range register value is the inverse of range. user should limit all i/o spaces to 256 bytes per pci 2.1 spec. if qsr bit 0 is set, defines pci base address 0.
section 4 pci 9080 registers ? plx technology, inc., 1997 page 71 version 1.02 4.4.14 (las1ba; pci:f4h, loc:174h) local address space 1 local base address (remap) register table 4-46. (las1ba; pci:f4h, loc:174h) local address space 1 local base address (remap) register field description read write value after reset 0 space 1 enable. value of 1 enables decoding of pci addresses for direct slave access to local space 1. value of 0 disables decoding. if this bit is set to 0, the pci bios may not allocate (assign) the base address for space 1. note: must be set to 1 for any direct slave access to space 1. yes yes 0 1 reserved. yes no 0 3:2 if local space 1 is mapped into memory space, bits are not used. if mapped into i/o space, bit is included with bits [31:4] for remapping. yes yes 0 31:4 remap of pci address to local address space 1 into a local address space. the bits in this register remap (replace) the pci address bits used in decode as the local address bits. yes yes 0 note: remap address value must be multiple of range ( not the range register). 4.4.15 (lbrd1; pci:f8h, loc:178h) local address space 1 bus region descriptor register table 4-47. (lbrd1; pci:f8h, loc:178h) local address space 1 bus region descriptor register field description read write value after reset 1:0 memory space 1 local bus width. value of 00 indicates bus width of 8 bits, a value of 01 indicates bus width of 16 bits and a value of 10 or 11 indicates bus width of 32 bits. yes yes s = 01 j = 11 c = 11 5:2 memory space 1 internal wait states (data to data; 0-15 wait states). yes yes 0 6 memory space 1 ready input enable. value of 1 enables ready input. value of 0 disables ready input. yes yes 0 7 memory space 1 bterm# input enable. value of 1 enables bterm# input. value of 0 disables bterm# input. if this bit is set to 0, pci 9080 bursts four lword maximum at a time. yes yes 0 8 memory space 1 burst enable. value of 1 enables bursting. value of 0 disables bursting. if burst is disabled, the local bus performs continuous single cycles for burst pci read/write cycles. yes yes 0 9 memory space 1 prefetch disable. if mapped into memory space, 0 enables read prefetching. value of 1 disables prefetching. if prefetching is disabled, pci 9080 disconnects after each memory read. yes yes 0 10 read prefetch count enable. when set to 1 and memory prefetching is enabled, pci 9080 prefetches up to the number of lwords specified in the prefetch count. when set to 0, pci 9080 ignores the count is ignored and continues prefetching until terminated by the pci bus. yes yes 0 14:11 prefetch counter. number of lwords to prefetch during memory read cycles (0-15). yes yes 0 31:15 reserved. yes no 0
section 4 pci 9080 registers ? plx technology, inc., 1997 page 72 version 1.02 4.5 runtime registers 4.5.1 (mbox0; pci:40h or 78h, loc:c0h) mailbox register 0 table 4-48. (mbox0; pci:40h or 78h, loc:c0h) mailbox register 0 field description read write value after reset 31:0 32 bit mailbox register. yes yes 0 note: mailbox register 0 is replaced by the inbound queue port when the i 2 o feature is enabled (bit 0 in the qsr register is set). mailbox register 0 is always accessible at pci address 78h and local address c0h. 4.5.2 (mbox1; pci:44h or 7ch, loc:c4h) mailbox register 1 table 4-49. (mbox1; pci:44h or 7ch, loc:c4h) mailbox register 1 field description read write value after reset 31:0 32 bit mailbox register. yes yes 0 note: mailbox register 1 is replaced by the outbound queue port when the i 2 o feature is enabled (bit 0 in the qsr register is set). mailbox register 1 is always accessible at pci address 7ch and local address c4h. 4.5.3 (mbox2; pci:48h, loc:c8h) mailbox register 2 table 4-50. (mbox2; pci:48h, loc:c8h) mailbox register 2 field description read write value after reset 31:0 32 bit mailbox register. yes yes 0 4.5.4 (mbox3; pci:4ch, loc:cch) mailbox register 3 table 4-51. (mbox3; pci:4ch, loc:cch) mailbox register 3 field description read write value after reset 31:0 32 bit mailbox register. yes yes 0 4.5.5 (mbox4; pci:50h, loc:d0h) mailbox register 4 table 4-52. (mbox4; pci:50h, loc:d0h) mailbox register 4 field description read write value after reset 31:0 32 bit mailbox register. yes yes 0
section 4 pci 9080 registers ? plx technology, inc., 1997 page 73 version 1.02 4.5.6 (mbox5; pci:54h, loc:d4h) mailbox register 5 table 4-53. (mbox5; pci:54h, loc:d4h) mailbox register 5 field description read write value after reset 31:0 32 bit mailbox register. yes yes 0 4.5.7 (mbox6; pci:58h, loc:d8h) mailbox register 6 table 4-54. (mbox6; pci:58h, loc:d8h) mailbox register 6 field description read write value after reset 31:0 32 bit mailbox register. yes yes 0 4.5.8 (mbox7; pci:5ch, loc:dch) mailbox register 7 table 4-55. (mbox7; pci:5ch, loc:dch) mailbox register 7 field description read write value after reset 31:0 32 bit mailbox register. yes yes 0 4.5.9 (p2ldbell; pci:60h, loc:e0h) pci to local doorbell register table 4-56. (p2ldbell; pci:60h, loc:e0h) pci to local doorbell register field description read write value after reset 31:0 doorbell register. a pci master can write to this register and generate a local interrupt to the local processor. the local processor can then read this register to determine which doorbell bit was asserted. pci master sets a doorbell by writing 1 to a particular bit. the local processor can clear a doorbell bit by writing 1 to that bit position. yes yes/clr 0 4.5.10 (l2pdbell; pci:64h, loc:e4h) local to pci doorbell register table 4-57. (l2pdbell; pci:64h, loc:e4h) local to pci doorbell register field description read write value after reset 31:0 doorbell register. the local processor can write to this register and generate a pci interrupt. a pci master can then read this register to determine which doorbell bit was asserted. the local processor sets a doorbell by writing 1 to a particular bit. pci master can clear a doorbell bit by writing 1 to that bit position. yes yes/clr 0
section 4 pci 9080 registers ? plx technology, inc., 1997 page 74 version 1.02 4.5.11 (intcsr; pci:68h, loc:e8h) interrupt control/status register table 4-58. (intcsr; pci:68h, loc:e8h) interrupt control/status register field description read write value after reset 0 enable local bus lserr#. value of 1 enables pci 9080 to assert lserr# interrupt output when pci bus target abort or master abort status bit is set in the pci status configuration register. yes yes 0 1 enable local bus lserr# when pci parity error occurs during pci 9080 master transfer or pci 9080 slave access or outbound free list fifo overflow init. yes yes 0 2 generate pci bus serr#. when this bit is set to 0, writing a 1 generates a pci bus serr#. yes yes 0 3 mailbox interrupt enable. value of 1 enables a local interrupt to be generated when the pci bus writes to mailbox registers 0-3. to clear the local interrupt, the local master must read the mailbox. used in conjunction with local interrupt enable. yes yes 0 7:4 reserved. yes no 0 8 pci interrupt enable. value of 1 enables pci interrupts. yes yes 1 9 pci doorbell interrupt enable. value of 1 enables doorbell interrupts. used in conjunction with pci interrupt enable. clearing the doorbell interrupt bits that caused the interrupt also clears the interrupt. yes yes 0 10 pci abort interrupt enable. value of 1 enables a master abort or master detect of a target abort to generate a pci interrupt. used in conjunction with pci interrupt enable. clearing the abort status bits also clears the pci interrupt. yes yes 0 11 pci local interrupt enable. value of 1 enables a local interrupt input to generate a pci interrupt. use in conjunction with pci interrupt enable. clearing the local bus cause of the interrupt also clears the interrupt. yes yes 0 12 retry abort enable. value of 1 enables pci 9080 to treat 256 master consecutive retries to a target as a target abort. value of 0 enables pci 9080 to attempt master retries indefinitely. note: for diagnostic purposes only. yes yes 0 13 value of 1 indicates pci doorbell interrupt is active. yes no 0 14 value of 1 indicates pci abort interrupt is active. yes no 0 15 value of 1 indicates local interrupt is active (linti#). yes no 0 16 local interrupt output enable. value of 1 enables local interrupt output. yes yes 1 17 local doorbell interrupt enable. value of 1 enables doorbell interrupts. used in conjunction with local interrupt enable. clearing the local doorbell interrupt bits that caused the interrupt also clears the interrupt. yes yes 0 18 local dma channel 0 interrupt enable. value of 1 enables dma channel 0 interrupts. used in conjunction with local interrupt enable. clearing the dma status bits also clears the interrupt. yes yes 0 19 local dma channel 1 interrupt enable. value of 1 enables dma channel 1 interrupts. used in conjunction with local interrupt enable. clearing the dma status bits also clears the interrupt. yes yes 0 20 value of 1 indicates local doorbell interrupt is active. yes no 0 21 value of 1 indicates dma ch 0 interrupt is active. yes no 0 22 value of 1 indicates dma ch 1 interrupt is active. yes no 0 23 value of 1 indicates bist interrupt is active. bist (built-in self test) interrupt is generated by writing 1 to bit 6 of the pci configuration bist register. clearing bit 6 clears the interrupt. refer to the bist register for a description of self test. (refer to table 4-18.) yes no 0
section 4 pci 9080 registers ? plx technology, inc., 1997 page 75 version 1.02 table 4-58. (intcsr; pci:68h, loc:e8h) interrupt control/status register (continued) field description read write value after reset 24 value of 0 indicates a direct master was the bus master during a master or target abort. (not valid until abort occurs.) yes no 1 25 value of 0 indicates dma ch 0 was the bus master during a master or target abort. (not valid until abort occurs.) yes no 1 26 value of 0 indicates dma ch 1 was the bus master during a master or target abort. (not valid until abort occurs.) yes no 1 27 value of 0 indicates a target abort was generated by the pci 9080 after 256 consecutive master retries to a target. (not valid until abort occurs.) yes no 1 28 value of 1 indicates pci wrote data to the mailbox #0. enabled only if mboxintenb is enabled (bit 3 high). yes no 0 29 value of 1 indicates pci wrote data to the mailbox #1. enabled only if mboxintenb is enabled (bit 3 high). yes no 0 30 value of 1 indicates pci wrote data to the mailbox #2. enabled only if mboxintenb is enabled (bit 3 high). yes no 0 31 value of 1 indicates pci wrote data to the mailbox #3. enabled only if mboxintenb is enabled (bit 3 high). yes no 0
section 4 pci 9080 registers ? plx technology, inc., 1997 page 76 version 1.02 4.5.12 (cntrl; pci:6ch, loc:ech) serial eeprom control, pci command codes, user i/o control, init control register table 4-59. (cntrl; pci:6ch, loc:ech) serial eeprom control, pci command codes, user i/o control, init control register field description read write value after reset 3:0 pci read command code for dma. this pci command is sent out during dma read cycles. yes yes 1110 7:4 pci write command code for dma. this pci command is sent out during dma write cycles. yes yes 0111 11:8 pci memory read command code for direct master. this pci command is sent out during direct master read cycles. yes yes 0110 15:12 pci memory write command code for direct master. this pci command is sent out during direct master write cycles. yes yes 0111 16 general purpose output. value of 1 causes usero output to go high. value of 0 causes user0 output to go low. yes yes 1 17 general purpose input. value of 1 indicates useri input pin is high. value of 0 indicates useri pin is low. yes no 23:18 reserved. yes no 0 24 serial eeprom clock for local or pci bus reads or writes to serial eeprom. toggling this bit generates a serial eeprom clock. (refer to the manufacturers data sheet for the particular serial eeprom being used.) yes yes 0 25 serial eeprom chip select. for local or pci bus reads or writes to serial eeprom, setting this bit to 1 provides the serial eeprom chip select. yes yes 0 26 write bit to serial eeprom. for writes, this output bit is the input to the serial eeprom. clocked into the serial eeprom by the serial eeprom clock. yes yes 0 27 read serial eeprom data bit. for reads, this input bit is the output of the serial eeprom. clocked out of the serial eeprom by the serial eeprom clock. yes no 28 serial eeprom present. value of 1 indicates a serial eeprom is present. yes no 0 29 reload configuration registers. when this bit is set to 0, writing a 1 causes pci 9080 to reload the local configuration registers from serial eeprom. yes yes 0 30 pci adapter software reset. value of 1 holds the local bus logic in the pci 9080 reset and lreseto# asserted. the contents of the pci configuration registers and shared run time registers will not be reset. software reset can only be cleared from the pci bus. (local bus remains reset until this bit is cleared.) yes yes 0 31 local init status. value of 1 indicates local init done. responses to pci accesses are retrys until this bit is set. while input pin nb# is asserted low, this bit is forced to 1. yes yes 0
section 4 pci 9080 registers ? plx technology, inc., 1997 page 77 version 1.02 4.5.13 (pcihidr; pci:70h, loc:f0h) pci permanent configuration id register table 4-60. (pcihidr; pci:70h, loc:f0h) pci permanent configuration id register field description read write value after reset 15:0 permanent vendor id. identifies device manufacturer. note: hardcoded to the pci sig issued vendor id of plx (10b5h). yes no 10b5h 31:16 permanent device id. identifies the particular device. note: hardcoded to the plx part number for pci interface chip pci 9080. yes no 9080h 4.5.14 (pcihrev; pci:74h, loc:f4h) pci permanent revision id register table 4-61. (pcihrev; pci:74h, loc:f4h) pci permanent revision id register field description read write value after reset 7:0 permanent revision id. note: hardcoded to the silicon revision of the pci 9080. yes no current rev #
section 4 pci 9080 registers ? plx technology, inc., 1997 page 78 version 1.02 4.6 dma registers 4.6.1 (dmamode0; pci:80h, loc:100h) dma channel 0 mode register table 4-62. (dmamode0; pci:80h, loc:100h) dma channel 0 mode register field description read write value after reset 1:0 local bus width. value of 00 indicates bus width of 8 bits, a value of 01 indicates bus width of 16 bits and a value of 10 or 11 indicates bus width of 32 bits. yes yes s = 01 j = 11 c = 11 5:2 internal wait states (data to data). yes yes 0 6 ready input enable. value of 1 enables ready input. value of 0 disables ready input. yes yes 0 7 bterm# input enable. value of 1 enables bterm# input. value of 0 disables bterm# input. if this bit is set to 0, pci 9080 bursts four lword maximum at a time. yes yes 0 8 local burst enable. value of 1 enables bursting. value of 0 disables local bursting. if burst is disabled, the local bus performs continuous single cycles for burst pci read/write cycles. yes yes 0 9 chaining. value of 1 indicates chaining mode is enabled. for chaining mode, the dma source address, destination address and byte count are loaded from memory in pci or local address spaces. value of 0 indicates nonchaining mode is enabled. yes yes 0 10 done interrupt enable. value of 1 enables interrupt when done. value of 0 disables interrupt when done. if dma clear count mode is enabled, the interrupt wont occur until the byte count is cleared. yes yes 0 11 local addressing mode. value of 1 indicates local address la[31:2] to be held constant. value of 0 indicates local address is incremented. yes yes 0 12 demand mode. value of 1 causes dma controller to operate in demand mode. in demand mode, the dma controller transfers data when its dreq[1:0]# input is asserted. it asserts dack[1:0]# to indicate the current local bus transfer is in response to the dreq[1:0]# input. dma controller transfers lwords (32 bits) of data. this may result in multiple transfers for an 8- or 16-bit bus. yes yes 0 13 write and invalidate mode for dma transfers. when set to 1, pci 9080 performs write and invalidate cycles to the pci bus. pci 9080 supports write and invalidate sizes of 8 or 16 lwords. the size is specified in the pci cache line size register. if a size other than 8 or 16 is specified, pci 9080 performs write transfers rather than write and invalidate transfers. transfers must start and end at the cache line boundaries. yes yes 0 14 dma eot (end of transfer) enable. value of 1 enables eot[1:0]# input pin. value of 0 disables eot[1:0]# input pin. (refer to section 3.7.6.1, end of transfer (eot0# or eot1#) input.) yes yes 0 15 dma stop data transfer mode. value of 0 sends a blast to terminate dma transfer. value of 1 indicates an eot asserted or dreq[1:0]# negated during demand mode dma terminates the dma transfer. (refer to section 3.7.6.1, end of transfer (eot0# or eot1#) input.) yes yes 0 16 dma clear count mode. when set to 1, the byte count in each chaining descriptor, if it is in local memory, is cleared when the corresponding dma transfer is complete. note: if chaining descriptor is in pci memory, the count is not cleared. yes yes 0 17 dma channel 0 interrupt select. value of 1 routes the dma channel 0 interrupt to the pci interrupt. value of 0 routes the dma channel 0 interrupt to the local bus interrupt. yes yes 0 31:18 reserved. yes no 0
section 4 pci 9080 registers ? plx technology, inc., 1997 page 79 version 1.02 4.6.2 (dmapadr0; pci:84h, loc:104h) dma channel 0 pci address register table 4-63. (dmapadr0; pci:84h, loc:104h) dma channel 0 pci address register field description read write value after reset 31:0 pci address register. indicates from where in the pci memory space the dma transfers (reads or writes) start. yes yes 0 4.6.3 (dmaladr0; pci:88h, loc:108h) dma channel 0 local address register table 4-64. (dmaladr0; pci:88h, loc:108h) dma channel 0 local address register field description read write value after reset 31:0 local address register. indicates from where in the local memory space the dma transfers (reads or writes) start. yes yes 0 4.6.4 (dmasiz0; pci:8ch, loc:10ch) dma channel 0 transfer size (bytes) register table 4-65. (dmasiz0; pci:8ch, loc:10ch) dma channel 0 transfer size (bytes) register field description read write value after reset 22:0 dma transfer size (bytes). indicates number of bytes to be transferred during dma operation. yes yes 0 31:23 reserved. yes no 0 4.6.5 (dmadpr0; pci:90h, loc:110h) dma channel 0 descriptor pointer register table 4-66. (dmadpr0; pci:90h, loc:110h) dma channel 0 descriptor pointer register field description read write value after reset 0 descriptor location. value of 1 indicates pci address space. value of 0 indicates local address space. yes yes 0 1 end of chain. value of 1 indicates end of chain. value of 0 indicates not end of chain descriptor. (same as nonchaining mode.) yes yes 0 2 interrupt after terminal count. value of 1 causes an interrupt to be generated after the terminal count for this descriptor is reached. value of 0 disables interrupts from being generated. yes yes 0 3 direction of transfer. value of 1 indicates transfers from local bus to pci bus. value of 0 indicates transfers from pci bus to local bus. yes yes 0 31:4 next descriptor address. quad word aligned (bits [3:0] = 0000). yes yes 0
section 4 pci 9080 registers ? plx technology, inc., 1997 page 80 version 1.02 4.6.6 (dmamode1; pci:94h, loc:114h) dma channel 1 mode register table 4-67. (dmamode1; pci:94h, loc:114h) dma channel 1 mode register field description read write value after reset 1:0 local bus width. value of 00 indicates bus width of 8 bits, a value of 01 indicates bus width of 16 bits and a value of 10 or 11 indicates bus width of 32 bits. yes yes s = 01 j = 11 c = 11 5:2 internal wait states (data to data). yes yes 0 6 ready input enable. value of 1 enables ready input. value of 0 disables ready input. yes yes 0 7 bterm# input enable. value of 1 enables bterm# input. value of 0 disables bterm# input. if this bit is set to 0, pci 9080 bursts four lword maximum at a time. yes yes 0 8 local burst enable. value of 1 enables bursting. value of 0 disables local bursting. if burst is disabled, the local bus performs continuous single cycles for burst pci read/write cycles. yes yes 0 9 chaining. value of 1 indicates chaining mode enabled. for chaining mode, the dma source address, destination address and byte count are loaded from memory in pci or local address spaces. value of 0 indicates nonchaining mode enabled. yes yes 0 10 done interrupt enable. value of 1 enables interrupt when done. value of 0 disables interrupt when done. if dma clear count mode is enabled, the interrupt wont occur until the byte count is cleared. yes yes 0 11 local addressing mode. value of 1 indicates local address la[31:2] to be held constant. value of 0 indicates local address is incremented. yes yes 0 12 demand mode. value of 1 causes dma controller to operate in demand mode. in demand mode, the dma controller transfers data when its dreq[1:0]# input is asserted. it asserts dack[1:0]# to indicate the current local bus transfer is in response to the dreq[1:0]# input. dma controller transfers lwords (32 bits) of data. this may result in multiple transfers for an 8- or 16-bit bus. yes yes 0 13 write and invalidate mode for dma transfers. when set to 1, pci 9080 performs write and invalidate cycles to the pci bus. pci 9080 supports write and invalidate sizes of 8 or 16 lwords. the size is specified in the pci cache line size register. if a size other than 8 or 16 is specified, pci 9080 performs write transfers rather than write and invalidate transfers. transfers must start and end at the cache line boundaries. yes yes 0 14 dma eot (end of transfer) enable. value of 1 enables eot[1:0]# input pin. value of 0 disables eot[1:0]# input pin. (refer to section 3.7.6.1, end of transfer (eot0# or eot1#) input.) yes yes 0 15 dma stop data transfer mode. value of 0 blast terminates dma transfer. value of 1 indicates eot. in demand dma mode, if this bit is set to a value of 1, assertion of eot causes dma controller to terminate following the current data phase (blast may or may not be asserted). if bit is not set, and eot asserted, the dma controller completes current data phase and potentially a following data phase in which blast is asserted. (refer to section 3.7.6.1, end of transfer (eot0# or eot1#) input.) yes yes 0 16 dma clear count mode. when set to 1, the byte count in each chaining descriptor, if it is in local memory, is cleared when the corresponding dma transfer is complete. note: if chaining descriptor is in pci memory, the count is not cleared. yes yes 0 17 dma channel 1 interrupt select. value of 1 routes the dma channel 1 interrupt to the pci interrupt. value of 0 routes the dma channel 1 interrupt to the local bus interrupt. yes yes 0 31:18 reserved. yes no 0
section 4 pci 9080 registers ? plx technology, inc., 1997 page 81 version 1.02 4.6.7 (dmapadr1; pci:98h, loc:118h) dma channel 1 pci address register table 4-68. (dmapadr1; pci:98h, loc:118h) dma channel 1 pci address register field description read write value after reset 31:0 pci data address register. indicates from where in the pci memory space the dma transfers (reads or writes) start. yes yes 0 4.6.8 (dmaladr1; pci:9ch, loc:11ch) dma channel 1 local address register table 4-69. (dmaladr1; pci:9ch, loc:11ch) dma channel 1 local address register field description read write value after reset 31:0 local data address register. indicates from where in the local memory space the dma transfers (reads or writes) start. yes yes 0 4.6.9 (dmasiz1; pci:a0h, loc:120h) dma channel 1 transfer size (bytes) register table 4-70. (dmasiz1; pci:a0h, loc:120h) dma channel 1 transfer size (bytes) register field description read write value after reset 22:0 dma transfer size (bytes). indicates the number of bytes to transfer during a dma operation. yes yes 0 31:23 reserved. yes no 0 4.6.10 (dmadpr1; pci:a4h, loc:124h) dma channel 1 descriptor pointer register table 4-71. (dmadpr1; pci:a4h, loc:124h) dma channel 1 descriptor pointer register field description read write value after reset 0 descriptor location. value of 1 indicates pci address space. value of 0 indicates local address space. yes yes 0 1 end of chain. value of 1 indicates end of chain. value of 0 indicates not end of chain descriptor. (same as nonchaining mode.) yes yes 0 2 interrupt after terminal count. value of 1 causes an interrupt to be generated after the terminal count for this descriptor is reached. value of 0 disables interrupts from being generated. yes yes 0 3 direction of transfer. value of 1 indicates transfers from local bus to pci bus. value of 0 indicates transfers from pci bus to local bus. yes yes 0 31:4 next descriptor address. quad word aligned (bits [3:0] = 0000). yes yes 0
section 4 pci 9080 registers ? plx technology, inc., 1997 page 82 version 1.02 4.6.11 (dmacsr0; pci:a8h, loc:128h) dma channel 0 command/status register table 4-72. (dmacsr0; pci:a8h, loc:128h) dma channel 0 command/status register field description read write value after reset 0 channel 0 enable. value of 1 enables channel to transfer data. value of 0 disables channel from starting a dma transfer and if in the process of transferring data suspend transfer (pause). yes yes 0 1 channel 0 start. writing 1 to this bit causes channel to start transferring data if the channel is enabled. no yes/set 0 2 channel 0 abort. writing 1 to this bit causes channel to abort the current transfer. channel enable bit must be cleared. channel complete bit is set when the abort is complete. no yes/set 0 3 clear interrupt. writing 1 to this bit clears channel 0 interrupts. no yes/clr 0 4 channel 0 done. value of 1 indicates channels transfer is complete. value of 0 indicates channels transfer is not complete. yes no 1 7:5 reserved. yes no 0 4.6.12 (dmacsr1; pci:a9h, loc:129h) dma channel 1 command/status register table 4-73. (dmacsr1; pci:a9h, loc:129h) dma channel 1 command/status register field description read write value after reset 0 channel 1 enable. value of 1 enables channel to transfer data. value of 0 disables channel from starting a dma transfer and if in the process of transferring data suspend transfer (pause). yes yes 0 1 channel 1 start. writing 1 to this bit causes channel to start transferring data if channel is enabled. no yes/set 0 2 channel 1 abort. writing 1 to this bit causes channel to abort the current transfer. channel enable bit must be cleared. channel complete bit is set when the abort is complete. no yes/set 0 3 clear interrupt. writing 1 to this bit clears channel 1 interrupts. no yes/clr 0 4 channel 1 done. value of 1 indicates this channels transfer is complete. value of 0 indicates channels transfer is not complete. yes no 1 7:5 reserved. yes no 0 4.6.13 (dmaarb; pci:ach, loc:12ch) dma arbitration register same as mode/arbitration register (marbr) at address (pci:08h)(loc:88h) (refer to table 4-35).
section 4 pci 9080 registers ? plx technology, inc., 1997 page 83 version 1.02 4.6.14 (dmathr; pci:b0h, loc:130h) dma threshold register table 4-74. (dmathr; pci:b0h, loc:130h) dma threshold register field description read write value after reset 3:0 dma channel 0 pci to local almost full (c0plaf). number of full entries (divided by two, minus one) in fifo before requesting local bus for writes. (c0plaf+1) + (c0plae+1) should be fifo depth of 32. yes yes 0 7:4 dma channel 0 local to pci almost empty (c0lpae). number of empty entries (divided by two, minus one) in fifo before requesting local bus for reads. (c0lpaf+1) + (c0lpae+1) should be fifo depth of 32. yes yes 0 11:8 dma channel 0 local to pci almost full (c0lpaf). number of full entries (divided by two, minus one) in fifo before requesting local bus for writes. yes yes 0 15:12 dma channel 0 pci to local almost empty (c0plae). number of empty entries (divided by two, minus one) in fifo before requesting local bus for reads. yes yes 0 19:16 dma channel 1 pci to local almost full (c1plaf). number of full entries (divided by two, minus one) in fifo before requesting local bus for writes. (c1plaf+1) + (c1plae+1) should be fifo depth of 16. yes yes 0 23:20 dma channel 1 local to pci almost empty (c1lpae). number of empty entries (divided by two, minus one) in fifo before requesting local bus for reads. (c1plaf+1) + (c1plae+1) should be fifo depth of 16. yes yes 0 27:24 dma channel 1 local to pci almost full (c1lpaf). number of full entries (divided by two, minus one) in fifo before requesting local bus for writes. yes yes 0 31:28 dma channel 1 pci to local almost empty (c1plae). number of empty entries (divided by two, minus one) in fifo before requesting local bus for reads. yes yes 0 note: if the number of entries needed is x, then value is one less than half the number of entries (that is, x/2 C 1).
section 4 pci 9080 registers ? plx technology, inc., 1997 page 84 version 1.02 4.7 messaging queue registers 4.7.1 (oplfis; pci:30h, loc:b0) outbound post list fifo interrupt status register table 4-75. (oplfis; pci:30h, loc:b0) outbound post list fifo interrupt status register field description read write value after reset 2:0 reserved. yes no 0 3 outbound post list fifo interrupt. this bit is set when the outbound post list fifo is not empty. this bit is not effected by the interrupt mask bit. yes no 0 31:4 reserved. yes no 0 4.7.2 (oplfim; pci:34h, loc:b4) outbound post list fifo interrupt mask register table 4-76. (oplfim; pci:34h, loc:b4) outbound post list fifo interrupt mask register field description read write value after reset 2:0 reserved. yes no 0 3 outbound post list fifo interrupt mask. interrupt is masked when this bit is set. yes yes 1 31:4 reserved. yes no 0 4.7.3 (iqp; pci:40h) inbound queue port register table 4-77. (iqp; pci:40h) inbound queue port register field description read write value after reset 31:0 value written by pci master is stored into the inbound post list fifo, which is located in local memory at the address pointed to by the queue base address + fifo size + inbound post head pointer. from the time of the pci write until the local memory write and update of the inbound post queue head pointer, further accesses to this register result in a retry. a local interrupt is generated when the inbound post list fifo is not empty. when the port is read by the pci master, the value is read from the inbound free list fifo, which is located in local memory at the address pointed to by the queue base address + inbound free tail pointer. if fifo is empty, a value of fffffffh is returned. pci pci 0
section 4 pci 9080 registers ? plx technology, inc., 1997 page 85 version 1.02 4.7.4 (oqp; pci:44h) outbound queue port register table 4-78. (oqp; pci:44h) outbound queue port register field description read write value after reset 31:0 value written by pci master is stored into the outbound free list fifo, which is located in local memory at the address pointed to by the queue base address + (3*fifo size) + outbound free head pointer. from the time of the pci write until the local memory write and update of the outbound free head pointer, further accesses to this register result in a retry. if fifo fills up, a local lserr interrupt is generated. when the port is read by the pci master, the value is read from the outbound post list fifo, which is located in local memory at the address pointed to by the queue base address + (2*fifo size) + outbound post tail pointer. if fifo is empty, a value of fffffffh is returned. a pci interrupt is generated if outbound post list fifo is not empty. pci pci 0 4.7.5 (mqcr; pci:c0h, loc:140h) messaging queue configuration register table 4-79. (mqcr; pci:c0h, loc:140h) messaging queue configuration register field description read write value after reset 0 queue enable. value of 1 allows accesses to the inbound and outbound queue ports. if cleared to 0, writes are accepted but ignored and reads return ffffffff. all pointer initialization and frame allocation should be completed before enabling this bit. yes yes 0 5:1 circular fifo size. defines the size of one of the circular fifos. each of the four fifos are the same size. each fifo entry is one 32 bit word. fifo size encoding max entries fifo total fifo 5:1 per fifo size memory 00001 4k entries 16 kb 64 kb 00010 8k entries 32 kb 128 kb 00100 16k entries 64 kb 256 kb 01000 32k entries 128 kb 512 kb 10000 64k entries 256 kb 1 mb yes yes 00001 31:6 reserved. yes no 0 4.7.6 (qbar; pci:c4h, loc:144h) queue base address register table 4-80. (qbar; pci:c4h, loc:144h) queue base address register field description read write value after reset 19:0 reserved. yes no 0 31:20 queue base address. local memory base address of the inbound and outbound queues (four contiguous and equal size fifos). queue base address must be aligned on a 1 mb boundary. yes yes 0
section 4 pci 9080 registers ? plx technology, inc., 1997 page 86 version 1.02 4.7.7 (ifhpr; pci:c8h, loc:148h) inbound free head pointer register table 4-81. (ifhpr; pci:c8h, loc:148h) inbound free head pointer register field description read write value after reset 1:0 reserved. yes no 0 19:2 inbound free head pointer. local memory offset for inbound free list fifo. this register is initialized as (0*fifo size) and maintained by the local cpu software. yes yes 0 31:20 queue base address. yes no 0 4.7.8 (iftpr; pci:cch, loc:14ch) inbound free tail pointer register table 4-82. (iftpr; pci:cch, loc:14ch) inbound free tail pointer register field description read write value after reset 1:0 reserved. yes no 0 19:2 inbound free tail pointer. local memory offset for inbound free list fifo. this register is initialized as (0*fifo size) by the local cpu software. it is maintained by the mu hardware and is incremented modulo the fifo size. yes yes 0 31:20 queue base address. yes no 0 4.7.9 (iphpr; pci:d0h, loc:150h) inbound post head pointer register table 4-83. (iphpr; pci:d0h, loc:150h) inbound post head pointer register field description read write value after reset 1:0 reserved. yes no 0 19:2 inbound post head pointer. local memory offset for inbound post list fifo. this register is initialized as (1*fifo size) by the local cpu software. it is maintained by the mu hardware and is incremented modulo the fifo size. yes yes 0 31:20 queue base address. yes no 0 4.7.10 (iptpr; pci:d4h, loc:154h) inbound post tail pointer register table 4-84. (iptpr; pci:d4h, loc:154h) inbound post tail pointer register field description read write value after reset 1:0 reserved. yes no 0 19:2 inbound post tail pointer. local memory offset for inbound post list fifo. this register is initialized as (1*fifo size) and maintained by the local cpu software. yes yes 0 31:20 queue base address. yes no 0
section 4 pci 9080 registers ? plx technology, inc., 1997 page 87 version 1.02 4.7.11 (ofhpr; pci:d8h, loc:158h) outbound free head pointer register table 4-85. (ofhpr; pci:d8h, loc:158h) outbound free head pointer register field description read write value after reset 1:0 reserved. yes no 0 19:2 outbound free head pointer. local memory offset for outbound free list fifo. this register is initialized as (3*fifo size) by the local cpu software and is maintained by the mu hardware and is incremented modulo the fifo size. yes yes 0 31:20 queue base address. yes no 0 4.7.12 (oftpr; pci:dch, loc:15ch) outbound free tail pointer register table 4-86. (oftpr; pci:dch, loc:15ch) outbound free tail pointer register field description read write value after reset 1:0 reserved. yes no 0 19:2 outbound free tail pointer. local memory offset for outbound free list fifo. this register is initialized as (3*fifo size) and maintained by the local cpu software. yes yes 0 31:20 queue base address. yes no 0 4.7.13 (ophpr; pci:e0h, loc:160h) outbound post head pointer register table 4-87. (ophpr; pci:e0h, loc:160h) outbound post head pointer register field description read write value after reset 1:0 reserved. yes no 0 19:2 outbound post head pointer. local memory offset for outbound post list fifo. this register is initialized as (2*fifo size) and maintained by the local cpu software. yes yes 0 31:20 queue base address. yes no 0 4.7.14 (optpr; pci:e4h, loc:164h) outbound post tail pointer register table 4-88. (optpr; pci:e4h, loc:164h) outbound post tail pointer register field description read write value after reset 1:0 reserved. yes no 0 19:2 outbound post tail pointer. local memory offset for outbound post list fifo. this register is initialized as (2*fifo size) and maintained by the mu hardware and is incremented modulo the fifo size. yes yes 0 31:20 queue base address. yes no 0
section 4 pci 9080 registers ? plx technology, inc., 1997 page 88 version 1.02 4.7.15 (qsr; pci:e8h, loc:168h) queue status/control register table 4-89. (qsr; pci:e8h, loc:168h) queue status/control register field description read write value after reset 0i 2 0 decode enable. when this bit is set, mailbox registers 0 and 1 are replaced by the inbound and outbound queue port registers and redefines space 1 as pci base address 0 to be accessed by pcibar0. former space 1 registers f0, f4, and f8 should be programmed to configure their shared i 2 0 memory space, defined as pci base address 0. yes yes 0 1 queue local space select. when this bit is set to 0, use local address space 0 bus region descriptor for queue accesses. when this bit is set to 1, use local address space 1 bus region descriptor for queue accesses. yes yes 0 2 outbound post list fifo prefetch enable. when this bit is set, prefetching occurs from the outbound post list fifo if not empty. yes yes 0 3 inbound free list fifo prefetch enable. when this bit is set, prefetching occurs from the inbound free list fifo if not empty. yes yes 0 4 inbound post list fifo interrupt mask. interrupt is masked when bit is set. yes yes 1 5 inbound post list fifo interrupt. this bit is set when the inbound post list fifo is not empty. this bit is not affected by the interrupt mask bit. yes no 0 6 outbound free list fifo overflow interrupt mask. interrupt is masked when bit is set. yes yes 1 7 outbound free list fifo overflow interrupt. this bit is set when the outbound free list fifo becomes full. a local lserr (nmi) interrupt is generated if enabled in the interrupt control/status register. writing 1 clears the interrupt. yes yes/clr 0 31:8 unused. yes no 0
section 5 pci 9080 pin description ? plx technology, inc., 1997 page 89 version 1.02 5. pin description 5.1 pin summary the tables in this section describe pci 9080 pins. table 5-2 through table 5-5 provide pin information common to all three local bus modes of operation (that is, c, j, and s modes): ? power and ground pin description ? serial eeprom interface pin description ? pci system bus interface pin description ? local bus mode and processor independent interface pin description the pins in table 5-6 through table 5-8 correspond to the local bus modes of the pci 9080: ? c bus mode interface pin description (32-bit address/32-bit data, nonmultiplexed) ? j bus mode interface pin description (32-bit address/32-bit data, multiplexed) ? s bus mode interface pin description (32-bit address/16-bit data, multiplexed) the following pins have internal pull-ups: admode, bigend#, bterm#, dreq[1:0]#, eedo, eesel, linti#, llock#, lreseti#, nb#, readyi#, s[2:0], short#, and waiti#. the following pins have internal pull-downs: breq, lholda, test, and useri. for a visual view of the chip pin out, refer to figure 7-3 in section 7.3, 9080 pin out (s, j, and c modes). table 5-1 lists the abbreviations used in this section to represent the various pin types. table 5-1. pin type abbreviations abbreviation pin type i/o input and output pin i input pin only o output pin only ts tri-state pin oc open collector pin tp totem pole pin sts sustained tri-state pin, driven high for one clk before float dts driven tri-state pin, driven high for one-half clk before float all local bus internal pull-ups go through a 2 k w resistor. all local bus internal pull-downs go through a 100 k w resistor. all local tri-state i/o pins should have external pull-ups (use 3 k w - 10 k w ). unspecified pins are not connected. note: for pci pins, do not pull up or down any pins unless the pci 9080 is being used in an embedded design. refer to the pci local bus specification , v2.1, page 123.
section 5 pci 9080 pin description ? plx technology, inc., 1997 page 90 version 1.02 5.2 pin out common to all bus modes table 5-2. power and ground pin description symbol signal name total pins pin type pin number function test test 1 i 49 test pin. pull high for test, low for normal operation. when test is pulled high, all outputs except usero (pin 27) are placed in tri-state. usero provides a nand-tree output when test is pulled high. vddl (core) power (+5 v) 6 i 53, 68, 105, 144, 157, 167 five volt power supply pins for core. liberal .01 f to .1 f decoupling capacitors should be placed near the pci 9080. vddh (pci) power (+5 v or +3.3 v) 3 i 38, 60, 83 power supply pins for pci bus pins. liberal .01 f to .1 f decoupling capacitors should be placed near the pci 9080. vddh (local) power (+5 v) 3 i 1, 124, 184 power supply pins for local bus pins. liberal .01 f to .1 f decoupling capacitors should be placed near the pci 9080. vss ground 20 i 22, 37, 45, 52, 59, 67, 75, 82, 90, 98, 104, 114, 123, 134, 143, 156, 166, 183, 193, 208 ground pins. table 5-3. serial eeprom interface pin description symbol signal name total pins pin type pin number function eecs serial eeprom chip select 1o tp 8 ma 176 serial eeprom chip select. eedi serial eeprom data in 1o tp 8 ma 172 write data to serial eeprom. eedo serial eeprom data out 1 i 171 read data from serial eeprom. eesk serial data clock 1 o tp 8 ma 173 serial eeprom clock. short# load short 1 i 174 when active low, only five 32-bit registers are loaded from the serial eeprom. when active high, all local configuration registers are also loaded from serial eeprom. eesel serial eeprom select 1 i 175 when high, use 93cs46 (1k bit) serial eeprom. when low, use 93cs56 (2k bit) serial eeprom. note: serial eeprom interface operates at the core voltage (+5 v). pci 9080 requires the use of a serial eeprom that can operate up to 1 mhz.
section 5 pci 9080 pin description ? plx technology, inc., 1997 page 91 version 1.02 table 5-4. pci system bus interface pin description symbol signal name total pins pin type pin number function ad[31:0] address and data 32 i/o ts pci 32-36, 39-44, 46-47, 76-81, 84-89, 91-97 all multiplexed on the same pci pins. a bus transaction consists of an address phase followed by one or more data phases. pci 9080 supports both read and write bursts. c/be[3:0]# bus command and byte enables 4 i/o ts pci 70-73 all multiplexed on the same pci pins. during the address phase of a transaction, c/be[3:0]# defines the bus command. during the data phase c/be[3:0]# are used as byte enables. refer to pci spec for further detail if needed. clk clock 1 i 54 provides timing for all transactions on pci and is an input to every pci device. pci operates up to 33 mhz. devsel# device select 1 i/o sts pci 64 when actively driven, indicates the driving device has decoded its address as the target of the current access. as an input, indicates whether any device on the bus is selected. frame# cycle frame 1 i/o sts pci 57 driven by the current master to indicate the beginning and duration of an access. frame# is asserted to indicate a bus transaction is beginning. while frame# is asserted, data transfers continue. when frame# is negated, the transaction is in the final data phase. gnt# grant 1 i 51 indicates to the agent that access to the bus is granted. every master has its own req# and gnt#. idsel initialization device select 1 i 63 used as a chip select during configuration read and write transactions. inta# interrupt a 1 o oc pci 55 used to request an interrupt. irdy# initiator ready 1 i/o sts pci 61 indicates the ability of the initiating agent (bus master) to complete the current data phase of the transaction. lock# lock 1 i/o sts pci 69 indicates an atomic operation that may require multiple transactions to complete. par parity 1 i/o ts pci 74 even parity across ad[31:0] and c/be[3:0]#. parity generation is required by all pci agents. par is stable and valid one clock after the address phase. for data phases, par is stable and valid one clock after either irdy# is asserted on a write transaction or trdy# is asserted on a read transaction. once par is valid, it remains valid until one clock after the completion of the current data phase. perr# parity error 1 i/o sts pci 65 reporting of data parity errors during all pci transactions, except during a special cycle. req# request 1 o pci 50 indicates to the arbiter that this agent needs to use the bus. every master has its own gnt# and req#. rst# reset 1 i 56 used to bring pci-specific registers, sequencers and signals to a consistent state. serr# systems error 1 o oc pci 66 reports address parity errors, data parity errors on the special cycle command, or any other system error where the result will be catastrophic. stop# stop 1 i/o sts pci 62 indicates the current target is requesting the master to stop the current transaction. trdy# target ready 1 i/o sts pci 58 indicates the ability of the target agent (selected device) to complete the current data phase of the transaction.
section 5 pci 9080 pin description ? plx technology, inc., 1997 page 92 version 1.02 table 5-5. local bus mode and processor independent interface pin description symbol signal name total pins pin type pin number function admode address decode mode 1i 20 determines how s[2:0] are used to access the pci 9080 internal registers. bigend# big endian select 1 i 48 can be asserted during the local bus address phase of a direct master transfer or a configuration register access to specify use of big endian byte ordering. big endian byte order for direct master transfers or configuration register accesses is also programmable through configuration registers. bpclko buffered pci clock output 1 o tp 8 ma 168 provides a buffered pci clock output. breq bus request 1 i 169 asserted to indicate a local bus master requires the bus. if enabled through the pci 9080 configuration registers, pci 9080 releases the bus during a dma transfer if this signal is asserted. breqo bus request out 1 o tp 8 ma 21 asserted to indicate the pci 9080 requires the bus to perform a direct pci to local bus access while a direct master access is pending on the local bus. it can be used with external logic to generate backoff to a local bus master. its operational parameters are set up through the pci 9080 configuration registers. btermo# burst terminate out 1 o dts 8 ma 28 asserted, along with readyo#, to request the break up of a burst and the start of a new address cycle (abort only). dack[1:0]# dma acknowledge outputs 2o tp 8 ma 25, 30 when a channel is programmed through the configuration registers to operate in demand mode, its dack output indicates a dma transfer is being executed. dack0# corresponds to pci 9080 dma ch 0 and dack1# to dma ch 1. dmpaf# direct master programmable almost full 1o tp 8 ma 8 direct master write fifo almost full status output. programmable through a configuration register. dp[3:0] data parity 4 i/o ts 8 ma 12-15 parity is even for each of up to 4 byte lanes on the local bus. parity is checked for writes to the pci 9080 or reads by the pci 9080. parity is generated for reads from the pci 9080 or writes by the pci 9080. dreq[1:0]# dma request inputs 2 i 24, 29 when a channel is programmed through the configuration registers to operate in demand mode, its dreq input serves as a dma request. dreq0# corresponds to pci 9080 dma ch 0 and dreq1# to dma ch 1. ldshold direct slave hold request 1 o tp 8 ma 165 asserted concurrent with lhold to indicate the pci 9080 is requesting use of the local bus in order to perform a direct slave transfer. linti# local interrupt in 1 i 151 when asserted low, causes a pci interrupt. linto# local interrupt out 1 o tp 8 ma 152 synchronous level output that remains asserted as long as an interrupt condition exists. if an edge level interrupt is required, disabling and then enabling local interrupts though the interrupt control/status register (refer to table 4-58) creates an edge if an interrupt condition still exists or a new interrupt condition occurs. llocko# bus lock 1 o tp 8 ma 7 indicates an atomic operation for a direct slave pci to local bus access may require multiple transactions to complete. lreseti# local reset input 1 i 150 resets the local bus portion of the pci 9080, the local configuration registers and the dma configuration registers. also causes local reset output to be asserted.
section 5 pci 9080 pin description ? plx technology, inc., 1997 page 93 version 1.02 table 5-5. local bus mode and processor independent interface pin description (continued) symbol signal name total pins pin type pin number function lserr# system error interrupt output 1 o tp 8 ma 23 synchronous level output that is asserted when the pci bus target abort or master abort status bit is set in the pci status configuration register. if an edge level interrupt is required, disabling and then enabling lserr# interrupts through the interrupt/control status creates an edge if an interrupt condition still exists or a new interrupt condition occurs. mode[1:0] bus mode 2 i 9, 10 selects the bus operation mode of the pci 9080: bit 1 bit 0 bus mode 00c 01j 10s 1 1 reserved nb# no local bus initialization 1i 26 externally forces local init done bit in the init control register to 1. init done bit is also programmable through local bus configuration accesses. pci 9080 issues retrys to all pci accesses until local init done bit is set. if this bit is not going to be set by a local processor, tie nb# low. pchk# data parity check 1 o tp 8 ma 16 parity is checked for writes to the pci 9080 or reads by the pci 9080. parity is checked for each byte lane with its byte enable asserted. asserted in the clock cycle following the data being checked if a parity error is detected. s[2:0] address select 3 i 17-19 if admode is high, internal pci 9080 registers are selected when la[31:29] match s[2:0]. if admode is low, the internal pci 9080 registers are selected when s0 is asserted low. useri user input 1 1 31 general purpose input that can be read from the pci 9080 configuration registers. usero user output 1 o tp 12 ma 27 general purpose output controlled from the pci 9080 configuration registers. waiti# wait input 1 i 6 can be asserted to cause the pci 9080 to insert wait states for local direct master accesses to the pci bus. can be thought of as a ready input for direct master accesses. waito# wait out 1 o ts 8 ma 149 indicates the pci 9080 programmable wait state generator status. waito# is asserted when wait states are being caused by the internal wait state generator. can be thought of as an output providing ready out status.
section 5 pci 9080 pin description ? plx technology, inc., 1997 page 94 version 1.02 5.3 c bus mode pin out table 5-6. c bus mode interface pin description c mode bus symbol signal name total pins pin type pin number function ads# address strobe 1 i/o ts 12 ma 154 indicates a valid address and the start of a new bus access. asserted for the first clock of a bus access. blast# burst last 1 i/o ts 8 ma 155 signal driven by the current local bus master to indicate the last transfer in a bus access. bterm# burst terminate 1 i 146 for processors that burst up to four lwords. if bterm is disabled through the pci 9080 configuration registers, pci 9080 also bursts up to four lwords. if enabled, pci 9080 continues to burst until a bterm# input is asserted. bterm# is a ready input that breaks up a burst cycle and causes another address cycle to occur. used in conjunction with the pci 9080 programmable wait state generator. den# data enable 1 o ts 12 ma 145 used in conjunction with dt/r# to provide control for data transceivers attached to the local bus. dt/r# data transmit/receive 1 o ts 12 ma 138 used in conjunction with den# to provide control for data transceivers attached to the local bus. when asserted, the signal indicates the pci 9080 receives data. lw/r# write/read 1 i/o ts 12 ma 137 asserted low for reads and high for writes. llock# bus lock 1 i 153 indicates an atomic operation that may require multiple transactions to complete. used by the pci 9080 for direct local access to the pci bus. la[31:2] address bus 30 i/o ts 8 ma 136, 135, 133-125, 122-115, 113-106, 103-101 carries the upper 30 bits of the physical address bus. during bursts, la[31:2] increment to indicate successive data cycles. ld[31:0] data bus 32 i/o ts 8 ma 177-182, 185-192, 194-207, 2-5 carries 32, 16, or 8 bit data quantities depending on bus width configuration.
section 5 pci 9080 pin description ? plx technology, inc., 1997 page 95 version 1.02 table 5-6. c bus mode interface pin description (continued) c mode bus symbol signal name total pins pin type pin number function lbe[3:0]# byte enables 4 i/o ts 12 ma 139-142 encoded, based on configured bus width, as follows: 32-bit bus : for a 32-bit bus, the four byte enables indicate which of the four bytes are active during a data cycle: be3# byte enable 3ld[31:24] be2# byte enable 2ld[23:16] be1# byte enable 1ld[15:8] be0# byte enable 0ld[7:0] 16-bit bus: for a 16-bit bus, be3#, be1# and be0# are encoded to provide bhe#, la1, and ble#, respectively: be3# byte high enable (bhe#)ld[15:8] be2# not used be1# address bit 1 (la1) be0# byte low enable (ble#)ld[7:0] 8-bit bus: for an 8-bit bus, be1# and be0# are encoded to provide la1and la0, respectively: be3# not used be2# not used be1# address bit 1 (la1) be0# address bit 0 (la0) lclk local processor clock 1 i 160 local clock input. lhold hold request 1 o tp 8 ma 158 asserted to request use of the local bus. the local bus arbiter asserts lholda when control is granted. lholda hold acknowledge 1 i 159 asserted by the local bus arbiter when control is granted in response to lhold. the bus should not be granted to pci 9080 unless requested by lhold. lreseto# local bus reset out 1 o tp 8 ma 11 asserted when the pci 9080 chip is reset. used to drive the reset# input of the local processor. readyi# ready in 1 i 147 when the pci 9080 is a bus master, indicates that read data on the bus is valid or that a write data transfer is complete. used in conjunction with the pci 9080 programmable wait state generator. readyo# ready out 1 o dts 8 ma 148 when a local bus access is made to the pci 9080, indicates read data on the bus is valid or a write data transfer is complete. readyo# can be connected to readyi#. eot0# end of transfer for dma ch 0 1 i 163 terminates the current dma ch 0 transfer. eot1# end of transfer for dma ch 1 1 i 164 terminates the current dma ch 1 transfer.
section 5 pci 9080 pin description ? plx technology, inc., 1997 page 96 version 1.02 5.4 j bus mode pin out table 5-7. j bus mode interface pin description j bus mode symbol signal name total pins pin type pin number function ale address latch enable 1 o ts 8 ma 161 asserted during the address phase and negated before the data phase. ads# address strobe 1 i/o ts 12 ma 154 indicates the valid address and the start of a new bus access. asserted for the first clock of a bus access. blast# burst last 1 i/o ts 8 ma 155 signal driven by the current local bus master to indicate the last transfer in a bus access. bterm# burst terminate 1 i 146 for processors that burst up to four lwords. if bterm is disabled through the pci 9080 configuration registers, pci 9080 also bursts up to four lwords. if enabled, pci 9080 continues to burst until a bterm# input is asserted. bterm# is a ready input that breaks up a burst cycle and causes another address cycle to occur. used in conjunction with the pci 9080 programmable wait state generator. den# data enable 1 i/o ts 12 ma 145 as an input, den# must only be asserted during data phases. for processor systems in which ads# is not asserted during the data phase, den# can be pulled high. as an output, dt/r# is used in conjunction with den# to provide control for data transceivers attached to the local bus. dt/r# data transmit/receive 1 o ts 12 ma 138 used in conjunction with den# to provide control for data transceivers attached to the local bus. when asserted the signal indicates the pci 9080 receives data. lw/r# write/read 1 i/o ts 12 ma 137 asserted low for reads and high for writes. labs[3:2] address bus burst 2 i/o ts 8 ma 162,163 carries the word address of the 32 bit memory address. these bits are incremented during a burst access. lad[31:0] address/data bus 32 i/o ts 8 ma 136, 135, 133-125, 122-115, 113-106, 103-99 during the address phase, the bus carries the upper 30 bits of the physical address bus. during the data phase, the bus carries 32 bits of data.
section 5 pci 9080 pin description ? plx technology, inc., 1997 page 97 version 1.02 table 5-7. j bus mode interface pin description (continued) j mode bus symbol signal name total pins pin type pin number function lbe[3:0]# byte enables 4 i/o ts 12 ma 139-142 byte enables are encoded based on configured bus width as follows: 32-bit bus: for a 32-bit bus, the four byte enables indicate which of the four bytes are active during a data cycle: be3# byte enable 3lad[31:24] be2# byte enable 2lad[23:16] be1# byte enable 1lad[15:8] be0# byte enable 0lad[7:0] 16-bit bus: for a 16-bit bus, be3#, be1# and be0# are encoded to provide bhe#, la1, and ble#, respectively: be3# byte high enable (bhe#)lad[15:8] be2# not used be1# address bit 1 (la1) be0# byte low enable (ble#)lad[7:0] 8-bit bus: for an 8-bit bus, be1# and be0# are encoded to provide la1and la0, respectively: be3# not used be2# not used be1# address bit 1 (la1) be0# address bit 0 (la0) lclk system clock 1 i 160 local clock input. lhold hold request 1 o tp 8 ma 158 asserted to request use of the local bus. the local bus arbiter asserts lholda when control is granted. lholda hold acknowledge 1 i 159 asserted by the local bus arbiter when control is granted in response to lhold. the bus should not be granted to pci 9080 unless requested by lhold. llock# bus lock 1 i 153 indicates an atomic operation that may require multiple transactions to complete. used by the pci 9080 for direct local access to the pci bus. lreseto# local bus reset out 1 o tp 8 ma 11 asserted when the pci 9080 chip is reset. readyi# ready in 1 i 147 when the pci 9080 is a bus master, readyi# is used to indicate read data on the bus is valid or a write data transfer is complete. readyi# is used in conjunction with the pci 9080 programmable wait state generator. readyo# ready out 1 o dts 8 ma 148 when a local bus access is made to the pci 9080, indicates that read data on the bus is valid or that a write data transfer is complete. readyo# can be connected to readyi#. eot0# end of transfer for dma ch 0 1 i 4 terminates the current dma ch 0 transfer. eot1# end of transfer for dma ch 1 1 i 5 terminates the current dma ch 1 transfer.
section 5 pci 9080 pin description ? plx technology, inc., 1997 page 98 version 1.02 5.5 s bus mode pin out table 5-8. s bus mode interface pin description s bus mode symbol signal name total pins pin type pin number function ale address latch enable 1o ts 8 ma 161 asserted during the address phase and negated before the data phase. as# address strobe 1 i/o ts 12 ma 154 indicates valid address and the start of a new bus access. asserted for the first clock of a bus access. blast# burst last 1 i/o ts 8 ma 155 signal driven by the current local bus master to indicate the last transfer in a bus access. bterm# burst terminate 1 i 146 for processors that burst up to eight words and do not use bterm# input. if bterm is disabled through the pci 9080 configuration registers, pci 9080 also bursts up to eight words. if enabled, pci 9080 continues to burst until a bterm# input is asserted. bterm# breaks up a burst cycle and causes another address cycle to occur. used in conjunction with the pci 9080 programmable wait state generator. den# data enable 1 o ts 12 ma 145 used in conjunction with dt/r# to provide control for data transceivers attached to the local bus. dt/r# data transmit/receive 1 o ts 12 ma 138 used in conjunction with den# to provide control for data transceivers attached to the local bus. when asserted, the signal indicates the pci 9080 is receiving data. la[31:16] address bus 16 i/o ts 8 ma 136, 135, 133-125, 122-118 carries the upper 16 bits of the address. labs[3:1] address bus burst 3 i/o ts 8 ma 162-164 carries the word address of the 32 bit memory address. these bits are incremented during a burst access. lad[15:1],d0 address/data bus 16 i/o ts 8 ma 117-115, 113-106, 103-99 during the address phase, carries the lower physical address bits. during the data phase, carries 16 bits of data. lbe[1:0]# byte enables 2 i/o ts 12 ma 141,142 indicate which of the two bytes are active during a data cycle. lclk local clock 1 i 160 local clock input. note: for i960 a s processor systems, clk2 input. i960 a s processors reset# input must be connected to pci 9080 lreseto# output. this enables pci 9080 to determine the phase of the 2x clock processor. lhold hold request 1 o tp 8 ma 158 asserted to request use of the local bus. the local bus arbiter asserts lholda when control is granted. lholda hold acknowledge 1 i 159 asserted by the local bus arbiter when control is granted in response to lhold. the bus should not be granted to the pci 9080 unless requested by lhold.
section 5 pci 9080 pin description ? plx technology, inc., 1997 page 99 version 1.02 table 5-8. s bus mode interface pin description (continued) s bus mode symbol signal name total pins pin type pin number function llock# bus lock 1 i 153 indicates an atomic operation that may require multiple transactions to complete. used by the pci 9080 for direct local access to the pci bus. lreseto# local bus reset out 1 o tp 8 ma 11 asserted when the pci 9080 chip is reset. note: for i960 a s processors, this output must be used to drive the reset input of the i960 a s processor. this enables pci 9080 to determine the phase of the 2x clock processor . lw/r# write/read 1 i/o ts 12 ma 137 asserted low for reads and high for writes. readyi# ready in 1 i 147 when the pci 9080 is a bus master, readyi# is used to indicate read data on the bus is valid or a write data transfer is complete. readyi# is used in conjunction with the pci 9080 programmable wait state generator. readyo# ready out 1 o dts 8 ma 148 when a local bus access is made to the pci 9080, indicates that read data on the bus is valid or that a write data transfer is complete. readyo# can be connected to readyi#. eot0# end of transfer for dma ch 0 1 i 4 terminates the current dma ch 0 transfer. eot1# end of transfer for dma ch 1 1 i 5 terminates the current dma ch 1 transfer.
section 6 pci 9080 electrical specifications ? plx technology, inc., 1997 page 100 version 1.02 6. electrical specifications table 6-1. absolute maximum ratings specification maximum rating storage temperature -65 c to +150 c ambient temperature with power applied -55 c to +125 c supply voltage to ground -0.5 v to +7.0 v input voltage (vin) vss -0.5 v, vdd +0.5 v output voltage (vout) vss -0.5 v, vdd +0.5 v table 6-2. operating ranges input voltage (vin) ambient temperature supply voltage (vdd) min max 0 c to +70 c 5 v 5% vss vdd table 6-3. operating ranges parameter test conditions pin type typical value units cin vin = 2.0 v, f = 1 mhz input 5 pf cout vout = 2.0 v, f = 1 mhz output 10 pf table 6-4. electrical characteristics estimated over operating range parameter description test conditions min max units voh output high voltage ioh = -4.0 ma 2.4 vdd v vol output low voltage vdd = min vin = vih or vil iol per tables vss 0.4 v vih input high level 2.0 5.5 v vil input low level -0.5 0.3 v voh3 pci 3.3 v output high voltage vdd = min ioh = -4.0 ma v vol3 pci 3.3 v output low voltage vin = vih or vil iol per tables v vih3 pci 3.3 v input high level v vil3 pci 3.3 v input low level v ili input leakage current vss vin vdd, vdd = max -10 +10 m a ioz tri-state output leakage current vdd = max, vss vin vdd -10 +10 m a icc power supply current vdd=5.25 v, pclk=lclk=33 mhz ? 130 ma
section 6 pci 9080 electrical specifications ? plx technology, inc., 1997 page 101 version 1.02      
  figure 6-1. pci 9080 local input setup and hold waveform table 6-5. ac electrical characteristics (local inputs) estimated over operating range signals (synchronous inputs) c l = 50 pf, vcc = 5.0 5% t setup (nsec) t hold (nsec) (worst case) ads# 7 1.5 blast# 5 2.3 bterm# 7 1.5 dp[3:0] 9 1.5 dreq[1:0]# 6 1.5 la[31:0] 10 1.5 lbe[3:0]# 8 1.5 ld[31:0] 9 1.5 lw/r# 9 1.5 readyi# 8 1.5 input clocks min max local clock input frequency 0 40 mhz pci clock input frequency 0 33 mhz
section 6 pci 9080 electrical specifications ? plx technology, inc., 1997 page 102 version 1.02  
 
 

    figure 6-2. pci 9080 local output delay table 6-6. ac electrical characteristics (local outputs) estimated over operating range signals (synchronous outputs) c l = 50 pf, vcc = 5.0 5% output t valid (max) ads# 14.5 ale (j and s modes) (address setup and hold relative to ale negative edge) blast# 16 breqo 13 btermo# 15 dack[1:0]# 14 den# 13 dmpaf# dp[3:0] 20 dt/r# 16 la[31:2] 20 labs[3:1] (s mode), labs[3:2] (j mode) 12 lbe[3:0]# 16 ld[31:0] 20 lhold 14 linto# 13 lserr# 14 lw/r# 14.5 pchk# 13 readyo# 14 waito# 20 note: all t valid (mins) values are greater than 5 nsec.
section 7 pci 9080 package, signal, and pin out specs ? plx technology, inc., 1997 page 103 version 1.02 7. package, signal, and pin out specs 7.1 package mechanical dimensions for 208 pqfp, q jc = 5 c/watt  
          
                 
    
figure 7-1. package mechanical dimensions
section 7 pci 9080 package, signal, and pin out specs ? plx technology, inc., 1997 page 104 version 1.02 7.2 typical pci bus master adapter   
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figure 7-2. typical pci bus master adapter
section 7 pci 9080 package, signal, and pin out specs ? plx technology, inc., 1997 page 105 version 1.02 7.3 9080 pin out (s, j, and c modes) refer to section 5, pin description, for a complete description of each pin used in s, j, and c modes.  
 
          
          
           
                          
 
         
          
           
                          
 
         
          
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%$ %% %& % % % % &! &" &# &$ &% && & & & & ! " # $ % &     ! " # $ % &     ! " # $ % &     ! " # $ %     #! # # " " " " "$ "# "" "! " " ! ! ! ! !$ !# !" !! ! !          $  #  "  !        $ # " !       $ # " !     & % $ # " !     & % $ # " !     & % $ # " !     & % $ # " ! & & & & && &% &$ &# &" &! % % % figure 7-3. pci 9080 pin out (s, j, and c modes)
section 8 pci 9080 timing diagrams ? plx technology, inc., 1997 page 106 version 1.02 8. timing diagrams the pci 9080 operates in three modes, selected through mode pins, corresponding to three bus typesc, j, and s. timing diagrams are provided for the three operating modes. for some functions, a timing diagram may only be provided for one mode of operation. even though a different mode is used, the timing diagram can be used to determine functionality. 8.1 list of timing diagrams initialization timing diagram 8-1. (c, j modes) pci rst# asserting local output lreseto# timing diagram 8-2. (s mode) two phase clock synchronization using lreseto# timing diagram 8-3. pci 9080 local bus arbitration timing diagram 8-4. pci 9080 1k serial eeprom pci initialization timing diagram 8-5. local interrupt (linti#) input asserting pci output inta# c mode direct slave timing diagram 8-6. (c mode) pci configuration write to pci 9080 pci configuration register timing diagram 8-7. (c mode) pci configuration read to pci 9080 pci configuration register timing diagram 8-8. (c mode) pci configuration write to pci 9080 local configuration register timing diagram 8-9. (c mode) pci configuration read to pci 9080 local configuration register timing diagram 8-10. (c mode) direct slave single cycle read timing diagram 8-11. (c mode) direct slave single cycle write timing diagram 8-12. (c mode) pci 9080 dma or direct slave burst read from local bus, bterm enabled timing diagram 8-13. (c mode) dma or direct slave pci 9080 burst write to local bus, bterm enabled timing diagram 8-14. (c mode) direct slave pci to local burst read, bterm disabled timing diagram 8-15. (c mode) pci 9080 dma or direct slave burst write, bterm disabled timing diagram 8-16. (c mode) direct slave read with prefetch counter set to 5 timing diagram 8-17. (c mode) direct slave or dma burst write to 32 bit local bus suspended by breq input timing diagram 8-18. (c mode) direct slave burst read of five lwords with one wait state timing diagram 8-19. (c mode) direct slave burst of five lwords with one wait state timing diagram 8-20. (c mode) direct slave read 2.1 spec timing diagram 8-21. (c mode) direct slave read no flush mode (read ahead mode) timing diagram 8-22. (c mode) direct slave read of two lwords from 8-bit bus timing diagram 8-23. (c mode) pci 9080 dma or direct slave two lword burst write to 8 bit local bus timing diagram 8-24. (c mode) direct slave read of two lwords from 16-bit bus timing diagram 8-25. (c mode) pci 9080 dma or direct slave two lword burst write to 16 bit local bus timing diagram 8-26. (c mode) direct slave read of two lwords from 8 bit i/o local bus timing diagram 8-27. (c mode) direct slave write of two lwords to 8 bit i/o local bus timing diagram 8-28. (c mode) direct slave in bigend local bus with bigend# input or internal register setting timing diagram 8-29. (c mode) locked direct slave read followed by write and release (llocko#)
section 8 pci 9080 timing diagrams ? plx technology, inc., 1997 page 107 version 1.02 c mode direct master timing diagram 8-30. (c mode) local bus read from pci 9080 cfg registers timing diagram 8-31. (c mode) local bus write to pci 9080 cfg registers timing diagram 8-32. (c mode) local bus direct master single memory read timing diagram 8-33. (c mode) local bus direct master single memory write cycle timing diagram 8-34. (c mode) pci 9080 direct master memory read, 12 lword burst timing diagram 8-35. (c mode) pci 9080 direct master memory write of 12 lwords timing diagram 8-36. (c mode) pci 9080 direct master memory read with waiti# timing diagram 8-37. (c mode) pci 9080 direct master memory write with waiti# timing diagram 8-38. (c mode) pci 9080 direct master configuration readtype 1 or type 0 timing diagram 8-39. (c mode) pci 9080 direct master configuration writetype 1 or type 0 timing diagram 8-40. (c mode) local bus direct master read from pci i/o timing diagram 8-41. (c mode) direct master write to pci i/o timing diagram 8-42. (c mode) pci 9080 direct master memory readkeep bus timing diagram 8-43. (c mode) pci 9080 direct master memory readdrop bus timing diagram 8-44. (c mode) pci bus request (req#) delay during direct master write (8 pci clock delay) timing diagram 8-45. (c mode) direct master memory read, prefetch of 16 timing diagram 8-46. (c mode) direct master memory write and invalidate (mwi)cache line size of 8 timing diagram 8-47. (c mode) direct master in bigend local bus with bigend# input or interrupt timing diagram 8-48. (c mode) direct master burst, memory read cycles (changing lbe[3:0]#) timing diagram 8-49. (c mode) direct master five lword burst write (changing lbe[3:0]#) timing diagram 8-50. (c mode) direct master locked read followed by write and release (llock# and lock#) timing diagram 8-51. (c mode) breqo and deadlock c mode dma timing diagram 8-52. (c mode) dma aligned pci address to aligned local address, bterm disabled timing diagram 8-53. (c mode) dma aligned local address to aligned pci address, bterm enabled timing diagram 8-54. (c mode) dma aligned pci address to aligned local address (external generation of wait states) timing diagram 8-55. (c mode) read of dma chaining parameters from pci and local buses timing diagram 8-56. (c mode) pci 9080 dma read of chaining parameters from local bus timing diagram 8-57. (c mode) read of dma chaining parameters from pci bus (local to pci transfer) timing diagram 8-58. (c mode) single cycle dma demand mode pci to local timing diagram 8-59. (c mode) multiple cycle (burst) dma demand mode pci to local with no wait states timing diagram 8-60. (c mode) dma demand mode terminated with blast# (local to pci) timing diagram 8-61. (c mode) dma local to pci, terminated with eot[1:0]# timing diagram 8-62. (c mode) dma pci to local, terminated with eot[1:0]# timing diagram 8-63. (c mode) dma pci to local with local pause timer and local latency timer
section 8 pci 9080 timing diagrams ? plx technology, inc., 1997 page 108 version 1.02 j mode direct slave timing diagram 8-64. (j mode) pci 9080 direct slave burst read from local bus timing diagram 8-65. (j mode) pci 9080 direct slave burst write to local bus, bterm enabled timing diagram 8-66. (j mode) pci 9080 dma or direct slave burst write to local bus, bterm disabled timing diagram 8-67. (j mode) direct slave in bigend local bus with bigend# input or internal register setting timing diagram 8-68. (j mode) direct slave read v2.1 spec timing diagram 8-69. (j mode) direct slave read no flush mode (read ahead mode) timing diagram 8-70. (j mode) local bus read from pci 9080 cfg registers timing diagram 8-71. (j mode) local bus write to pci 9080 cfg registers j mode direct master timing diagram 8-72. (j mode) direct master read access from pci bus (keep pci bus if read fifo full mode), no pci disconnects timing diagram 8-73. (j mode) local bus direct master burst write access to pci bus, continuous if same clock rate and no pci disconnects timing diagram 8-74. (j mode) local bus direct master lock memory read access from pci bus followed by write and release j mode dma timing diagram 8-75. (j mode) pci 9080 dma local to pci timing diagram 8-76. (j mode) pci 9080 dma pci to local bus timing diagram 8-77. (j mode) dma read of chaining parameters timing diagram 8-78. (j mode) pci 9080 write to local bus breq asserted s mode timing diagram 8-79. (s mode) pci 9080 dma or direct slave two lword burst write to 16 bit local bus timing diagram 8-80. (s mode) local bus read from pci 9080 cfg registers timing diagram 8-81. (s mode) local bus write to pci 9080 cfg registers
section 8 pci 9080 timing diagrams ? plx technology, inc., 1997 page 109 version 1.02 8.2 initialization asynchronous 0ns 50ns 100ns 150ns 200ns clk rst# lclk lreseto# timing diagram 8-1. (c, j modes) pci rst# asserting local output lreseto# addr addr data 0ns 25ns 50ns 75ns 100ns 125ns 150 n lreseto# as# la[31:16] lad[15:1] lreseto# must be used to establish phase a relationship as shown. timing diagram 8-2. (s mode) two phase clock synchronization using lreseto# high if direct slave request must remain high until lhold goes low will not be re-asserted unitl lholda goes low pci 9080 drives bus |--- can go high 0ns 250ns 500ns lclk lhold ldshold lholda local bus timing diagram 8-3. pci 9080 local bus arbitration
section 8 pci 9080 timing diagrams ? plx technology, inc., 1997 page 110 version 1.02 11000000 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 bits [31:16] cfg register 0 hex bits [15:0] cfg register 0 hex d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 bits [31:16] of cfg register 8 hex continues d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 short: bits [15:0] mailbox 1 loc c4 hex long: bits [15:0] loc register 98 hex extra long: bits [15:0] subsystem vendor id 2c hex start bit 0 indicates eeprom present ----| internally pulled up last word eesk, eedo, eecs from cfg registers after completion of read continues 0us 5us 10us 15us 20us 25us eesk lreseto# eecs eedi eedo . eesk eedo . . . eesk(continues) eecs eedo timing diagram 8-4. pci 9080 1k serial eeprom pci initialization
section 8 pci 9080 timing diagrams ? plx technology, inc., 1997 page 111 version 1.02 cmd be addr response on the pci side data [3,15] 0ns 100ns 200ns 300ns 400ns 500 n clk frame# ad[31:0] c/be[3:0]# irdy# devsel# trdy# inta# lclk linti# timing diagram 8-5. local interrupt (linti#) input asserting pci output inta#
section 8 pci 9080 timing diagrams ? plx technology, inc., 1997 page 112 version 1.02 8.3 c mode 8.3.1 c mode direct slave 12 3 addr 567 cmd=b 8 4 be data 0ns 50ns 100ns 150ns 200ns 250ns clk frame# ad[31:0] c/be[3:0]# irdy# devsel# trdy# timing diagram 8-6. (c mode) pci configuration write to pci 9080 pci configuration register 123 addr 567 cmd=a 8 4 data read be 0ns 50ns 100ns 150ns 200ns 250ns 300n s clk frame# ad[31:0] c/be[3:0]# irdy# devsel# trdy# timing diagram 8-7. (c mode) pci configuration read to pci 9080 pci configuration register
section 8 pci 9080 timing diagrams ? plx technology, inc., 1997 page 113 version 1.02 123 addr 567 cmd=7 8 4 be data 0ns 50ns 100ns 150ns 200ns 250ns clk frame# ad[31:0] c/be[3:0]# irdy# devsel# trdy# timing diagram 8-8. (c mode) pci configuration write to pci 9080 local configuration register 12 3 addr 56 7 cmd=6 8 4 data read be 0ns 50ns 100ns 150ns 200ns 250ns clk frame# ad[31:0] c/be[3:0]# irdy# devsel# trdy# timing diagram 8-9. (c mode) pci configuration read to pci 9080 local configuration register
section 8 pci 9080 timing diagrams ? plx technology, inc., 1997 page 114 version 1.02 123 addr 56 7 cmd 8 be addr data 14 data 4 0ns 100ns 200ns 300ns 400ns 500ns clk frame# ad[31:0] c/be[3:0]# irdy# devsel# trdy# lclk lhold lholda ads# lw/r# blast# la[31:2] ld[31:0] readyi# timing diagram 8-10. (c mode) direct slave single cycle read
section 8 pci 9080 timing diagrams ? plx technology, inc., 1997 page 115 version 1.02 123 addr 567 cmd 8 4 be data addr data 0ns 250ns 500ns clk frame# ad[31:0] c/be[3:0]# irdy# devsel# trdy# lclk lhold lholda ads# lw/r# blast# la[31:2] ld[31:0] readyi# timing diagram 8-11. (c mode) direct slave single cycle write
section 8 pci 9080 timing diagrams ? plx technology, inc., 1997 page 116 version 1.02 d0 d1 d7 d4 d5 d6 a+14 a a+4 a+8 a+c a+10 a+18 a+1c d3 d2 lbe 0ns 100ns 200ns 300ns 400ns 500n s lclk lhold lholda ads# blast# lbe[3:0]# lw/r# ld[31:0] la[31:2] bterm# readyi# eight lword burst, no wait states, burst enabled, bterm enabled, 32 bit local bus. note: if bterm is disabled, a new ads cycle starts every quad lword boundary. timing diagram 8-12. (c mode) pci 9080 dma or direct slave burst read from local bus, bterm enabled
section 8 pci 9080 timing diagrams ? plx technology, inc., 1997 page 117 version 1.02 d0 d1 d10 d2 d3 d4 d8 d9 a+20 a a+4 a+8 a+c a+10 a+24 a+28 d5 d6 d7 a+14 a+18 a+1c bterm forces new ads# --> lbe 0ns 250ns 500ns lclk lhold lholda ads# blast# lbe[3:0]# lw/r# ld[31:0] la[31:2] bterm# readyi# eight lword burst, no wait states, burst enabled, bterm enabled, 32 bit local bus. note: if bterm is disabled, a new ads# cycle starts every quad lword boundary. timing diagram 8-13. (c mode) dma or direct slave pci 9080 burst write to local bus, bterm enabled
section 8 pci 9080 timing diagrams ? plx technology, inc., 1997 page 118 version 1.02 cmd be addr d0 d1 d2 d3 d4 +4 +8 +c +10 d0 d1 d2 d3 d4 d5 d6 d7 +14 +18 +1c addr 0ns 250ns 500ns clk frame# ad[31:0] c/be[3:0]# irdy# devsel# trdy# lclk lhold lholda ads# lw/r# blast# la[31:2] ld[31:0] readyi# bterm# no wait states, 32-bit bus, burst enabled, bterm disabled. unused read data is flushed using with local processor. timing diagram 8-14. (c mode) direct slave pci to local burst read, bterm disabled
section 8 pci 9080 timing diagrams ? plx technology, inc., 1997 page 119 version 1.02 0001 d2 d6 addr a+4 a+8 a+c d4 a+10 d0 d1 d3 d5 d7 d8 a+14 a+18 a+1c a+20 lbe = 1110 0ns 100ns 200ns 300ns 400ns 500ns lclk lhold lholda ads# blast# lbe[3:0]# lw/r# ld[31:0] la[31:2] bterm# readyi# no wait states, burst enabled, bterm disabled, 32 bit local bus. unaligned transfer results in new ads#. note: not all byte enables asserted or a quad boundary la[3:2]=11 results in a new ads#. timing diagram 8-15. (c mode) pci 9080 dma or direct slave burst write, bterm disabled
section 8 pci 9080 timing diagrams ? plx technology, inc., 1997 page 120 version 1.02 cmd be addr d0 d1 d2 d3 d4 +4 +8 +10 d0 d1 d2 d3 +c d4 addr 0ns 250ns 500ns clk frame# ad[31:0] c/be[3:0]# irdy# devsel# trdy# lclk lhold lholda ads# lw/r# blast# la[31:2] ld[31:0] readyi# timing diagram 8-16. (c mode) direct slave read with prefetch counter set to 5
section 8 pci 9080 timing diagrams ? plx technology, inc., 1997 page 121 version 1.02 does not change, unaligned has own cycle with ads# d0 d1 d9 d2 d3 d4 d6 d7 d8 d5 d10 +32 a +4 +8 +12 +16 +36 +20 +24 +28 a+40 0ns 250ns 500ns lclk lhold lholda ads# blast# lbe[3:0]# lw/r# ld[31:0] la[31:2] bterm# readyi# breq no wait states, burst enabled, bterm enabled, 32 bit local bus. owned by local processor or another bus master. dma continues where it left off. timing diagram 8-17. (c mode) direct slave or dma burst write to 32 bit local bus suspended by breq input
section 8 pci 9080 timing diagrams ? plx technology, inc., 1997 page 122 version 1.02 cmd be d4 d3 d2 d1 d0 addr +4 +8 +c +10 d0 d1 d2 d3 d4 d5 d6 d7 +1c +18 +14 addr 0ns 250ns 500ns 750ns clk frame# ad[31:0] c/be[3:0]# irdy# devsel# trdy# lclk lhold lholda ads# lw/r# blast# la[31:2] ld[31:0] readyi# five lwords, one wait state, burst enabled, bterm disabled. unused read data is flushed with local processor. timing diagram 8-18. (c mode) direct slave burst read of five lwords with one wait state
section 8 pci 9080 timing diagrams ? plx technology, inc., 1997 page 123 version 1.02 12 3 addr 56 7 cmd 8 4 +4 be do d1 d2 d3 d4 +8 +c +10 d1 d2 d3 d4 d0 a 0ns 250ns 500ns clk frame# ad[31:0] c/be[3:0]# irdy# devsel# trdy# lclk lhold lholda ads# blast# lw/r# la[31:2] ld[31:0] den# readyi# five lwords, one wait state, burst enabled, bterm enabled. timing diagram 8-19. (c mode) direct slave burst of five lwords with one wait state
section 8 pci 9080 timing diagrams ? plx technology, inc., 1997 page 124 version 1.02 cmd be addr aa lbe retry a cmd cmd be write is not allowed during delayed read retry delayed read retries d0 d1 d2 d3 d4 d5 d6 d7 d8 reads data +4 +8 +c +10 +14 +18 +1c d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 +20 +24 +28 +2c +30 +34 +38 +3c addr cmd d0 be write retries and completes 0ns 250ns 500ns 750ns 1000ns clk frame# ad[31:0] c/be[3:0]# irdy# devsel# trdy# perr# stop# lclk lhold lholda ads# blast# la[31:0] lad[31:0] lbe[3:0]# readyi# lw/r# disconnect immediately for a read. dont effect pending reads when a write cycle occurs. dont flush the read fifo if the pci read cycle completes. force retry on write if read pending. negate trdy# until space is available in the direct slave write fifo. timing diagram 8-20. (c mode) direct slave read 2.1 spec
section 8 pci 9080 timing diagrams ? plx technology, inc., 1997 page 125 version 1.02 cmd be addr addr lbe cmd be d1 d2 d3 d4 d5 d6 +4 +8 +c +10 +14 +18 +1c d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 +20 +24 +28 +2c +30 +34 +38 +3c +40 d16 d0 0ns 250ns 500ns 750ns 1000ns clk frame# ad[31:0] c/be[3:0]# irdy# devsel# trdy# lclk lhold lholda ads# blast# la[27:2] lad[31:0] lbe[3:0]# readyi# lw/r# timing diagram 8-21. (c mode) direct slave read no flush mode (read ahead mode)
section 8 pci 9080 timing diagrams ? plx technology, inc., 1997 page 126 version 1.02 cmd be addr d0 d1 a a + 4 de f be=a1, c c d e f [7:0] [15:8] [23:16] [31:24] [7:0] [15:8] [23:16] [31:24] 0ns 250ns 500ns clk frame# ad[31:0] c/be[3:0]# irdy# devsel# trdy# lclk lhold lholda ads# blast# lw/r# la[31:0] lbe[3:0]# ld[31:0] readyi# timing diagram 8-22. (c mode) direct slave read of two lwords from 8-bit bus
section 8 pci 9080 timing diagrams ? plx technology, inc., 1997 page 127 version 1.02 a a + 4 de f ccdef [7:0] [15:8] [23:16] [31:24] [15:8] [7:0] [23:16] [31:24] 0ns 100ns 200ns 300ns 400ns lhold lholda ads# blast# la[31:0] lbe[3:0]# ld[31:0] readyi# no wait states, bterm enabled. timing diagram 8-23. (c mode) pci 9080 dma or direct slave two lword burst write to 8 bit local bus
section 8 pci 9080 timing diagrams ? plx technology, inc., 1997 page 128 version 1.02 cmd be addr d0 d1 a [15:0] [31:16] [31:16] 4 646 a+4 [15:0] 0ns 100ns 200ns 300ns 400ns 500ns clk frame# ad[31:0] c/be[3:0]# irdy# devsel# trdy# lclk lhold lholda ads# lw/r# blast# la[31:2] ld[31:0] lbe[3:0]# readyi# timing diagram 8-24. (c mode) direct slave read of two lwords from 16-bit bus
section 8 pci 9080 timing diagrams ? plx technology, inc., 1997 page 129 version 1.02 a a + 4 646 4 d0[15:0] d0[31:16] d1[15:0] d1[31:16] 0ns 100ns 200ns 300ns lclk lhold lholda ads# blast# la[31:0] lbe[3:0]# ld[31:0] readyi# no wait states, bterm enabled. timing diagram 8-25. (c mode) pci 9080 dma or direct slave two lword burst write to 16 bit local bus
section 8 pci 9080 timing diagrams ? plx technology, inc., 1997 page 130 version 1.02 be ad0 a a + 4 cd [7:0] [15:8][23:16] [31:24] [7:0] [15:8][23:16] ad1 be ef [31:24] cd ef 0ns 250ns 500ns 750ns 1000ns 1250ns 1500ns clk frame# ad[31:0] c/be[3:0]# irdy# devsel# trdy# stop# lclk lhold lholda ads# blast# lw/r# la[31:0] lbe[3:0]# ld[31:0] readyi# timing diagram 8-26. (c mode) direct slave read of two lwords from 8 bit i/o local bus
section 8 pci 9080 timing diagrams ? plx technology, inc., 1997 page 131 version 1.02 be a d0 a a + 4 cd [7:0] [15:8] [23:16] [31:24] [7:0] [15:8] [23:16] a d1 be ef [31:24] cd ef 0ns 250ns 500ns 750ns 1000ns 1250ns 1500n s clk frame# ad[31:0] c/be[3:0]# irdy# devsel# trdy# stop# lclk lhold lholda ads# blast# lw/r# la[31:0] lbe[3:0]# ld[31:0] readyi# timing diagram 8-27. (c mode) direct slave write of two lwords to 8 bit i/o local bus
section 8 pci 9080 timing diagrams ? plx technology, inc., 1997 page 132 version 1.02 123 addr 567 cmd 8 4 be data= aabbccdd addr ddccbbaa 01234567 67452301 0ns 100ns 200ns 300ns 400ns 500ns clk frame# ad[31:0] c/be[3:0]# irdy# devsel# trdy# lclk lhold lholda ads# lw/r# blast# la[31:2] ld[31:0] readyi# timing diagram 8-28. (c mode) direct slave in bigend local bus with bigend# input or internal register setting
section 8 pci 9080 timing diagrams ? plx technology, inc., 1997 page 133 version 1.02 addr r byte enables d0 d1 w-a wbe w-data <-- can be deasserted after last data d0 addr d1 d2 d3 d4 +4 +8 +12 +16 +20 d5 d6 d7 +24 +28 d8 +32 w-data w-addr deasserted after detecting pci unlock ---> 0ns 250ns 500ns 750ns clk frame# ad[31:0] c/be[3:0]# irdy# devsel# trdy# lock# lclk lhold lholda ads# blast# la[31:2] ld[31:0] readyi# llocko# timing diagram 8-29. (c mode) locked direct slave read followed by write and release (llocko#)
section 8 pci 9080 timing diagrams ? plx technology, inc., 1997 page 134 version 1.02 8.3.2 c mode direct master dp0 dp1 data 0 data 1 cs or la[31:29] match s[2:0] 0ns 50ns 100ns 150ns 200ns 250ns lclk la[31:0] ld[31:0] cs# ads# lbe[3:0]# lw/r# blast# dp[3:0] readyo# timing diagram 8-30. (c mode) local bus read from pci 9080 cfg registers pchk0 pchk1 data 0 data 1 data 0 byte enables data 1 byte enables cs or la[31:29] match s[2:0] 0ns 50ns 100ns 150ns 200ns 250ns lclk la[31:0] ld[31:0] cs# ads# lbe[3:0]# lw/r# blast# readyo# pchk# timing diagram 8-31. (c mode) local bus write to pci 9080 cfg registers
section 8 pci 9080 timing diagrams ? plx technology, inc., 1997 page 135 version 1.02 a0 d0 d0 a cmd be lbe 0ns 100ns 200ns 300ns 400ns lclk la[31:2] lw/r# ads# blast# readyo# ld[31:0] lbe[3:0]# clk req# gnt# frame# ad[31:0] c/be[3:0]# devsel# irdy# trdy# timing diagram 8-32. (c mode) local bus direct master single memory read
section 8 pci 9080 timing diagrams ? plx technology, inc., 1997 page 136 version 1.02 a0 d0 d0 cmd be lbe a 0ns 100ns 200ns 300ns 400ns lclk la[31:2] lw/r# ads# blast# readyo# ld[31:0] lbe[3:0]# clk req# gnt# frame# ad[31:0] c/be[3:0]# devsel# irdy# trdy# timing diagram 8-33. (c mode) local bus direct master single memory write cycle
section 8 pci 9080 timing diagrams ? plx technology, inc., 1997 page 137 version 1.02 d0 d1 d2 d3 a d4 d5 d6 d7 d8 d9 d10 d11 addr cbe be d0 d8 d12 d16 d4 0ns 250ns 500ns 750ns lclk la[31:2] lw/r# ads# blast# readyo# ld[31:0] clk req# gnt# frame# ad[31:0] c/be[3:0]# devsel# irdy# trdy# timing diagram 8-34. (c mode) pci 9080 direct master memory read, 12 lword burst
section 8 pci 9080 timing diagrams ? plx technology, inc., 1997 page 138 version 1.02 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 left center r i a cmd d0 d3 d1 d4 d2 d5 d6 d11 d7 d10 d8 d9 be a 0ns 250ns 500ns 750 n lclk la[31:2] ld[31:0] lw/r# ads# blast# readyo# clk req# gnt# frame# ad[31:0] c/be[3:0]# devsel# irdy# trdy# timing diagram 8-35. (c mode) pci 9080 direct master memory write of 12 lwords
section 8 pci 9080 timing diagrams ? plx technology, inc., 1997 page 139 version 1.02 d0 d1 d2 d3 a d4 d5 d6 d7 d8 d9 d10 d11 0ns 250ns 500ns 750ns lclk la[31:2] lw/r# ads# blast# readyo# ld[31:0] waiti# clk req# gnt# frame# ad[31:0] c/be[3:0]# devsel# irdy# trdy# timing diagram 8-36. (c mode) pci 9080 direct master memory read with waiti#
section 8 pci 9080 timing diagrams ? plx technology, inc., 1997 page 140 version 1.02 d0 d1 d2 d3 a d4 d5 d6 d7 d8 d9 d10 d11 a d0 d11 d1 d10 d2 d5 d3 d6 d4 d7 cmd d8 d9 be 0ns 250ns 500ns 7 5 lclk la[31:2] lw/r# ads# blast# readyo# ld[31:0] waiti# clk req# gnt# frame# ad[31:0] c/be[3:0]# devsel# irdy# trdy# timing diagram 8-37. (c mode) pci 9080 direct master memory write with waiti#
section 8 pci 9080 timing diagrams ? plx technology, inc., 1997 page 141 version 1.02 a d0 d1 d2 a0 d0 cmd 0 disable 0ns 250ns 500ns 750ns lclk la[31:0] ld[31:0] lw/r# ads# blast# readyo# clk req# gnt# frame# ad[31:0] c/be[3:0]# devsel# irdy# trdy# timing diagram 8-38. (c mode) pci 9080 direct master configuration readtype 1 or type 0
section 8 pci 9080 timing diagrams ? plx technology, inc., 1997 page 142 version 1.02 a d0 d1 d2 a0 d0 cmd 0 disable 0ns 250ns 500ns lclk la[31:0] ld[31:0] lw/r# ads# blast# readyo# clk req# gnt# frame# ad[31:0] c/be[3:0]# devsel# irdy# trdy# timing diagram 8-39. (c mode) pci 9080 direct master configuration writetype 1 or type 0
section 8 pci 9080 timing diagrams ? plx technology, inc., 1997 page 143 version 1.02 a0 d0 d0 a cmd 0 a d1 d2 cmd 0 a1 d1 cmd 0 a2 d2 0ns 250ns 500ns 750ns 1000ns 1250ns lclk la[31:2] lw/r# ads# blast# readyo# ld[31:0] clk req# gnt# frame# ad[31:0] c/be[3:0]# devsel# irdy# trdy# stop# timing diagram 8-40. (c mode) local bus direct master read from pci i/o
section 8 pci 9080 timing diagrams ? plx technology, inc., 1997 page 144 version 1.02 a0 d0 d0 a cmd 0 a+4 d1 a+8 d2 a+c d3 cmd 0 a1 d1 cmd 0 a2 d2 cmd 0 a3 d3 0ns 250ns 500ns 750ns 1000ns lclk la[31:2] lw/r# ads# blast# readyo# ld[31:0] clk req# gnt# frame# ad[31:0] c/be[3:0]# devsel# irdy# trdy# timing diagram 8-41. (c mode) direct master write to pci i/o
section 8 pci 9080 timing diagrams ? plx technology, inc., 1997 page 145 version 1.02 d0 d1 d2 d3 a d4 d5 d6 d7 d8 d9 d10 d11 de-assert irdy# & keep bus d12d13 d14 d16 0ns 250ns 500ns 750ns 1000ns 1250ns 1500ns lclk la[31:2] ld[31:0] lw/r# ads# blast# readyo# waiti# clk req# gnt# frame# ad[31:0] c/be[3:0]# devsel# irdy# trdy# timing diagram 8-42. (c mode) pci 9080 direct master memory readkeep bus
section 8 pci 9080 timing diagrams ? plx technology, inc., 1997 page 146 version 1.02 d0 d2 addr d4 d6 d7 d8 d10 drop bus d12 d15 0ns 250ns 500ns 750ns 1000ns 1250ns 1500ns lclk la[31:2] ld[31:0] lw/r# ads# blast# readyo# waiti# clk req# gnt# frame# ad[31:0] c/be[3:0]# devsel# irdy# trdy# timing diagram 8-43. (c mode) pci 9080 direct master memory readdrop bus
section 8 pci 9080 timing diagrams ? plx technology, inc., 1997 page 147 version 1.02 addr cmd be be ra d0 d1 d2 d3 d0 d2 d3 1 2 3 4 5 6 7 8 9 10 11121314151617 1819 2021 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 d1 0ns 250ns 500ns lclk la[31:2] ld[31:0] lbe[3:0]# lw/r# ads# blast# readyo# clk req# gnt# frame# ad[31:0] c/be[3:0]# devsel# irdy# trdy# timing diagram 8-44. (c mode) pci bus request (req#) delay during direct master write (8 pci clock delay)
section 8 pci 9080 timing diagrams ? plx technology, inc., 1997 page 148 version 1.02 d0 d1 d2 d3 addr d4 d5 d6 d7 d8 d9 d10 d11 d0 d1 d3 d2 d4 d6 d5 d8 d7 d9 d11 d10 d12 d14 d13 d15 0ns 250ns 500ns 750ns lclk la[31:2] ld[31:0] lw/r# ads# blast# readyo# clk req# gnt# frame# ad[31:0] c/be[3:0]# devsel# irdy# trdy# timing diagram 8-45. (c mode) direct master memory read, prefetch of 16
section 8 pci 9080 timing diagrams ? plx technology, inc., 1997 page 149 version 1.02 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 d0 d1 d3 d2 d4 d6 d5 d8 d7 d9 d11 d10 d12 d14 d13 d15 addr a 0ns 250ns 500ns 750ns 1000ns lclk la[31:2] ld[31:0] lw/r# ads# blast# readyo# clk req# gnt# frame# ad[31:0] c/be[3:0]# devsel# irdy# trdy# timing diagram 8-46. (c mode) direct master memory write and invalidate (mwi)cache line size of 8
section 8 pci 9080 timing diagrams ? plx technology, inc., 1997 page 150 version 1.02 addr ddccbbaa 67452301 123 addr 567 cmd 8 4 be data= aabbccdd 01234567 9101112 0ns 100ns 200ns 300ns 400ns 500ns lclk lhold lholda ads# lw/r# blast# la[31:2] ld[31:0] readyi# clk frame# ad[31:0] c/be[3:0]# irdy# devsel# trdy# timing diagram 8-47. (c mode) direct master in bigend local bus with bigend# input or interrupt
section 8 pci 9080 timing diagrams ? plx technology, inc., 1997 page 151 version 1.02 a be 0 be=3 be=4 be=8 d0 d1 d2 d3 a0 d0 d1 d2 d3 cmd 0 be=9 d4 d4 d5 d6 d7 d8 d9 d10 d11 dm read - does not pass byte enable 0ns 250ns 500ns lclk la[31:2] lbe[3:0]# ld[31:0] lw/r# ads# blast# readyo# clk req# gnt# frame# ad[31:0] c/be[3:0]# devsel# irdy# trdy# timing diagram 8-48. (c mode) direct master burst, memory read cycles (changing lbe[3:0]#)
section 8 pci 9080 timing diagrams ? plx technology, inc., 1997 page 152 version 1.02 a cmd be=0 be=f be=0 be=a be=0 be=f be=0 be=a ad0d1d2d3 d1 d0 d2 d3 d4 be=c d4 be=c pass byte enable 0ns 100ns 200ns 300ns 400ns 500n lclk la[31:2] ld[31:0] lbe[3:0]# lw/r# ads# blast# readyo# clk req# gnt# frame# ad[31:0] c/be[3:0]# devsel# irdy# trdy# timing diagram 8-49. (c mode) direct master five lword burst write (changing lbe[3:0]#)
section 8 pci 9080 timing diagrams ? plx technology, inc., 1997 page 153 version 1.02 d0 d1 d2 d3 d0 ra cmd 0000 wa r-ra wd unlock --> <-- lock keep lock --> r-wa wd cmd 0ns 250ns 500ns 750ns lclk la[31:2] lw/r# llock# ads# blast# readyo# ld[31:0] clk req# gnt# frame# ad[31:0] c/be[3:0]# devsel# irdy# trdy# lock# timing diagram 8-50. (c mode) direct master locked read followed by write and release (llock# and lock#)
section 8 pci 9080 timing diagrams ? plx technology, inc., 1997 page 154 version 1.02 addr cmd byte enables addr d0 d0 d1 d2 direct slave proceeds direct master read direct slave read direct master will not gain pci bus until direct slave access completes (gnt# asserted , frame# de-asserted, irdy# de-asserted) <-- direct slave- breqo timer starts no direct master ready d3 d1 d2 0ns 250ns 500ns 750ns clk frame# ad[31:0] c/be[3:0]# irdy# devsel# trdy# req# lclk lhold lholda ads# la[31:2] ld[31:0] readyo# readyi# breqo breqo timer expires and asserts breqo note: for partial deadlock, pci retry timer bits [31:28] to indicate potential deadlock condition. of the local bus region descriptor register can be used to issue retrys to the pci master attempting external logic backs off direct master transfer and the direct slave access. asserts lholda to grant the local bus for a direct slave transfer. refer to section 3, functional description, for a description of deadlock. timing diagram 8-51. (c mode) breqo and deadlock
section 8 pci 9080 timing diagrams ? plx technology, inc., 1997 page 155 version 1.02 8.3.3 c mode dma cmd be addr d0 d1 d2 d3 d4 addr +4 +8 +c +10 d0 d1 d2 d3 d4 d5 d6 d7 +14 +18 +1c d5 d7 d6 0ns 250ns 500ns 750ns clk frame# ad[31:0] c/be[3:0]# irdy# devsel# trdy# lclk lhold lholda ads# lw/r# blast# la[31:2] ld[31:0] readyi# bterm# no wait states, 32-bit bus, burst enabled, bterm disabled. timing diagram 8-52. (c mode) dma aligned pci address to aligned local address, bterm disabled
section 8 pci 9080 timing diagrams ? plx technology, inc., 1997 page 156 version 1.02 addr d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 a d1 d11 d2 d5 d3 d10 d4 d9 d6 d8 d7 cmd d0 be 0ns 250ns 500ns 750ns 1000ns clk req# gnt# frame# ad[31:0] c/be[3:0]# devsel# irdy# trdy# lclk la[31:2] ld[31:0] lw/r# ads# blast# readyi# timing diagram 8-53. (c mode) dma aligned local address to aligned pci address, bterm enabled
section 8 pci 9080 timing diagrams ? plx technology, inc., 1997 page 157 version 1.02 123 addr 56 7 cmd 8 4 addr be do d1 d2 d3 d4 d0 d1 d2 d3 d4 0ns 250ns 500ns 750ns clk frame# ad[31:0] c/be[3:0]# irdy# devsel# trdy# lclk lhold lholda ads# blast# lw/r# la[31:2] ld[31:0] den# readyi# five lwords, one wait state, bterm enabled. timing diagram 8-54. (c mode) dma aligned pci address to aligned local address (external generation of wait states)
section 8 pci 9080 timing diagrams ? plx technology, inc., 1997 page 158 version 1.02 a be d0 d1 d3 a+4+8 d0 d1 2 wait states +12 +16 d2 d3 reading from the descriptor a1 d0 be d1 local to pci transfer d2 d2 d3 d0 d1 d2 d3 d1 d2 d1 d2 a2 d1 local to pci transfer 0ns 500ns 1000ns 1500ns 2000 n clk frame# ad[31:0] c/be[3:0]# irdy# devsel# trdy# lclk lhold lholda ads# blast# la[31:2] ld[31:0] lw/r# readyi# timing diagram 8-55. (c mode) read of dma chaining parameters from pci and local buses
section 8 pci 9080 timing diagrams ? plx technology, inc., 1997 page 159 version 1.02 lbe d1 d2 addr <--- pci 9080 drives bus d0 d3 0ns 100ns 200ns 300ns 400ns 500ns lclk lhold lholda ads# blast# lbe[3:0]# lw/r# la[31:2] ld[31:0] dt/r# den# readyi# first address a are bits [31:4] of next descriptor pointer register. d0: pci start address d1: local start address d2: transfer count (bytes) d3: next descriptor pointer no wait states. timing diagram 8-56. (c mode) pci 9080 dma read of chaining parameters from local bus
section 8 pci 9080 timing diagrams ? plx technology, inc., 1997 page 160 version 1.02 addr cmd be d0 d1 d3 addr(d1) +4 +8 d0 d1 2 wait states +12 +16 d2 d3 reading from the descriptor addr(d0) d0 cmd be d1 local to pci transfer d2 d2 d3 0ns 250ns 500ns 750ns clk frame# ad[31:0] c/be[3:0]# irdy# devsel# trdy# lclk lhold lholda ads# blast# la[31:2] ld[31:0] lw/r# readyi# timing diagram 8-57. (c mode) read of dma chaining parameters from pci bus (local to pci transfer)
section 8 pci 9080 timing diagrams ? plx technology, inc., 1997 page 161 version 1.02 d0 a dreq[1:0]# must be de-asserted to prevent burst ------------------------------> 0ns 100ns 200ns 300ns lclk lhold lholda ads# blast# lbe[3:0]# lw/r# ld[31:0] la[31:2] dreq[1:0]# dack[1:0]# readyi# no wait states. timing diagram 8-58. (c mode) single cycle dma demand mode pci to local
section 8 pci 9080 timing diagrams ? plx technology, inc., 1997 page 162 version 1.02 d0 a current data + last data transferred after dreq[1:0]# is de-asserted a+4 d1 0ns 100ns 200ns 300ns 400ns lclk lhold lholda ads# blast# lbe[3:0]# lw/r# ld[31:0] la[31:2] dreq[1:0]# dack[1:0]# readyi# no wait states, burst enabled, bterm enabled, 32 bit local bus. timing diagram 8-59. (c mode) multiple cycle (burst) dma demand mode pci to local with no wait states
section 8 pci 9080 timing diagrams ? plx technology, inc., 1997 page 163 version 1.02 d0 a dreq[1:0]# must be deasserted when blast# is de-asserted a+4 d1 0ns 50ns 100ns 150ns 200ns 250ns 300ns lclk lhold lholda ads# blast# lbe[3:0]# lw/r# ld[31:0] la[31:2] dreq[1:0]# dack[1:0]# readyi# no wait states, burst enabled, bterm enabled, 32 bit local bus. timing diagram 8-60. (c mode) dma demand mode terminated with blast# (local to pci)
section 8 pci 9080 timing diagrams ? plx technology, inc., 1997 page 164 version 1.02 addr +4 +8 +c +10 +14 +18 d0 d1 d2 d3 d4 d5 addr d0 d1 d2 d3 d4 d5 cmd be 0ns 250ns 500ns clk frame# ad[31:0] c/be[3:0]# irdy# devsel# trdy# lclk lhold lholda ads# blast# la[31:2] ld[31:0] lw/r# readyi# eot[1:0]# stop data transfer mode bit is not set. if this bit is set, there is no blast# and d5 is not transferred. see table 4-62[15] or table 4-67[15]. timing diagram 8-61. (c mode) dma local to pci, terminated with eot[1:0]#
section 8 pci 9080 timing diagrams ? plx technology, inc., 1997 page 165 version 1.02 addr cmd be d0 d1 d2 d3 d4 d5 d6 d7 addr +4 +8 d0 d1 0ns 250ns 500ns clk frame# ad[31:0] c/be[3:0]# irdy# devsel# trdy# lclk lhold lholda ads# blast# la[31:2] ld[31:0] lw/r# readyi# eot[1:0]# stop data transfer mode bit is not set. if this bit is set, there is no blast# and d5 is not transferred. see table 4-62[15] or table 4-67[15]. timing diagram 8-62. (c mode) dma pci to local, terminated with eot[1:0]#
section 8 pci 9080 timing diagrams ? plx technology, inc., 1997 page 166 version 1.02 cmd be d0 d1 d2 d3 d4 +4 +8 +10 d0 d1 d2 d3 +c d4 d7 d6 d5 d8 d9 d10 d11 d12 d13 d14 d15 d5 d6 d7 d8 +14 +18 +1c +20 addr 0ns 250ns 500ns 750ns clk frame# ad[31:0] c/be[3:0]# irdy# devsel# trdy# lclk lhold lholda ads# lw/r# blast# la[31:2] ld[31:0] readyi# latency timer = 7 clk, pause timer = 4 clk. pci 9080 has internally added another clock to the pause timer. therefore, the time when lhold is de-asserted to when it is re-asserted is 5 clks for a pause timer of 4 clk. timing diagram 8-63. (c mode) dma pci to local with local pause timer and local latency timer
section 8 pci 9080 timing diagrams ? plx technology, inc., 1997 page 167 version 1.02 8.4 j mode 8.4.1 j mode direct slave a does not change, unaligned has own cycle with ads# d0 d1 d7 d2 d3 d4 a+20 d5 d6 00 01 10 11 00 10 11 01 0ns 100ns 200ns 300ns 400ns 500ns lclk lhold lholda ldshold ads# ale blast# lbe[3:0]# lw/r# lad[31:0] lba[3:2] dt/r# den# bterm# readyi# eight lword burst, no wait states, burst enabled, bterm enabled, 32 bit local bus. note: if bterm is disabled, a new ads# cycle starts every quad lword boundary. timing diagram 8-64. (j mode) pci 9080 direct slave burst read from local bus
section 8 pci 9080 timing diagrams ? plx technology, inc., 1997 page 168 version 1.02 a does not change, unaligned has own cycle with ads# d0 d1 d7 d2 d3 d4 a+20 d5 d6 lad[3:2] lad[3:2] 0ns 100ns 200ns 300ns 400ns 500ns lclk lhold lholda ldshold ads# ale blast# lbe[3:0]# lw/r# lad[31:0] labs[3:2] dt/r# den# bterm# readyi# eight lword burst, no wait states, burst enabled, bterm enabled, 32 bit local bus. note: if bterm is disabled, a new ads# cycle starts every quad lword boundary. timing diagram 8-65. (j mode) pci 9080 direct slave burst write to local bus, bterm enabled
section 8 pci 9080 timing diagrams ? plx technology, inc., 1997 page 169 version 1.02 does not change, unaligned has own cycle with ads# 01 10 11 00 00 01 10 d7 11 a d0 d1 d2 d3 a+16 d4 d5 d6 0ns 250ns 500ns lclk lhold lholda ads# ale blast# lbe[3:0]# lw/r# lad[31:0] labs[3:2] dt/r# den# bterm# readyi# eight lword burst, no wait states, burst enabled, bterm disabled, 32 bit local bus. note: if bterm is disabled, a new ads# cycle starts every quad lword boundary. timing diagram 8-66. (j mode) pci 9080 dma or direct slave burst write to local bus, bterm disabled
section 8 pci 9080 timing diagrams ? plx technology, inc., 1997 page 170 version 1.02 123 addr 56 7 cmd 8 4 be data= aabbccdd addr ddccbbaa 01234567 67452301 0ns 100ns 200ns 300ns 400ns 500ns clk frame# ad[31:0] c/be[3:0]# irdy# devsel# trdy# lclk lhold lholda ldshold ads# ale lw/r# blast# lad[31:0] readyi# timing diagram 8-67. (j mode) direct slave in bigend local bus with bigend# input or internal register setting
section 8 pci 9080 timing diagrams ? plx technology, inc., 1997 page 171 version 1.02 cmd be addr addr addr lbe retry addr cmd cmd be write is not allowed during delayed read retry delayed read retries d0 d1 d2 d3 d4 d5 d6 d7 d8 reads data d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 addr cmd d0 be write retries and completes 0ns 250ns 500ns 750ns 1000ns clk frame# ad[31:0] c/be[3:0]# irdy# devsel# trdy# perr# stop# lclk lhold lholda ldshold ads# ale blast# lad[31:0] lbe[3:0]# readyi# dtr# den# wr# rd# lw/r# disconnect immediately for a read. dont effect pending reads when a write cycle occurs. dont flush the read fifo if the pci read cycle completes. force retry on write if read pending. negate trdy# until space is available in the direct slave write fifo. timing diagram 8-68. (j mode) direct slave read v2.1 spec
section 8 pci 9080 timing diagrams ? plx technology, inc., 1997 page 172 version 1.02 cmd be a addr lbe cmd be d1 d2 d3 d4 d5 d6 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 d16 d0 single cycle burst cycle 0ns 250ns 500ns 750ns 1000ns clk frame# ad[31:0] c/be[3:0]# irdy# devsel# trdy# lclk lhold lholda ldshold ads# ale blast# lad[31:0] lbe[3:0]# lrdyi# lw/r# dtr# den# timing diagram 8-69. (j mode) direct slave read no flush mode (read ahead mode)
section 8 pci 9080 timing diagrams ? plx technology, inc., 1997 page 173 version 1.02 addr dp0 dp1 data 0 data 1 cs or la[31:29] match s[2:0] 0ns 50ns 100ns 150ns 200ns 250n lclk lad[31:0] cs# ads# lbe[3:0]# lw/r# den# blast# dp[3:0] readyo# timing diagram 8-70. (j mode) local bus read from pci 9080 cfg registers pchk0 pchk1 data 0 data 1 data 0 byte enables data 1 byte enables cs or la[31:29] match s[2:0] addr 0ns 50ns 100ns 150ns 200ns 250ns lclk ld[31:0] cs# ads# lbe[3:0]# lw/r# blast# readyo# pchk# timing diagram 8-71. (j mode) local bus write to pci 9080 cfg registers
section 8 pci 9080 timing diagrams ? plx technology, inc., 1997 page 174 version 1.02 8.4.2 j mode direct master a0 d0 d1 d2 d3 a cmd 0 d0 d1 d2 d3 d4 d5 d6 d7 d8 d4 d5 d6 d7 d15 d9 d10 d8 d16 d11 d9 d10 d11 d12 d13 d14 0ns 250ns 500ns 750ns 1000ns lclk lad[31:0] lw/r# ads# blast# readyo# clk req# gnt# frame# ad[31:0] c/be[3:0]# devsel# irdy# trdy# unused d12-d16 are flushed from fifo. timing diagram 8-72. (j mode) direct master read access from pci bus (keep pci bus if read fifo full mode), no pci disconnects
section 8 pci 9080 timing diagrams ? plx technology, inc., 1997 page 175 version 1.02 <--- local address matches local direct master base address cmd 0 r-a d0 d1 d2 d3 d1 d0 d2 d3 d4 d8 d9 remapped a --> d5 d6 d7 d8 d9 d10 d11 d12 d4 d5 d6 d7 d14 d15 a all lbe[3:0]# = 0000, separate ads#/data cycle for partials with local processor d10 d11 d12 d13 d14 d15 0ns 250ns 500ns 750ns lclk ld[31:0] lbe[3:0]# lw/r# ads# blast# readyo# clk req# gnt# frame# ad[31:0] c/be[3:0]# devsel# irdy# trdy# timing diagram 8-73. (j mode) local bus direct master burst write access to pci bus, continuous if same clock rate and no pci disconnects
section 8 pci 9080 timing diagrams ? plx technology, inc., 1997 page 176 version 1.02 d0 d1 d2 d3 ra cmd 0 0 0 0 wa r-ra unlock --> <-- lock keep lock --> r-wa wd cmd d0 wd 0ns 250ns 500ns 750ns lclk lad[31:0] lw/r# llock# ads# den# blast# readyo# clk req# gnt# frame# ad[31:0] c/be[3:0]# devsel# irdy# trdy# lock# one lword burst (pre-read four mode). timing diagram 8-74. (j mode) local bus direct master lock memory read access from pci bus followed by write and release
section 8 pci 9080 timing diagrams ? plx technology, inc., 1997 page 177 version 1.02 8.4.3 j mode dma a does not change, unaligned has own cycle with ads# d0 d1 d7 d2 d3 d4 a+20 d5 d6 00 01 10 11 00 10 11 01 0ns 100ns 200ns 300ns 400ns 500ns lclk lhold lholda ads# ale blast# lbe[3:0]# lw/r# lad[31:0] labs[3:2] dt/r# den# bterm# readyi# eight lword burst, no wait states, burst enabled, bterm enabled, 32 bit local bus. note: if bterm is disabled, a new ads# cycle starts every quad lword boundary. timing diagram 8-75. (j mode) pci 9080 dma local to pci
section 8 pci 9080 timing diagrams ? plx technology, inc., 1997 page 178 version 1.02 a does not change, unaligned has own cycle with ads# d0 d1 d7 d2 d3 d4 a+20 d5 d6 lad[3:2] lad[3:2] 0ns 100ns 200ns 300ns 400ns 500ns lclk lhold lholda ads# ale blast# lbe[3:0]# lw/r# lad[31:0] labs[3:2] dt/r# den# bterm# readyi# eight lword burst, no wait states, burst enabled, bterm enabled, 32 bit local bus. note: if bterm is disabled, a new ads# cycle starts every quad lword boundary. timing diagram 8-76. (j mode) pci 9080 dma pci to local bus
section 8 pci 9080 timing diagrams ? plx technology, inc., 1997 page 179 version 1.02 a all zero a+4 a+8 a+c d0 d1 d2 d3 0ns 100ns 200ns 300ns 400ns 500ns lclk lhold lholda ads# ale blast# lbe[3:0]# lw/r# lad[31:0] dt/r# den# readyi# first address a are bits [31:4] of next descriptor pointer register. d0: pci start address d1: local start address d2: transfer count (bytes) d3: next descriptor pointer no wait states. timing diagram 8-77. (j mode) dma read of chaining parameters
section 8 pci 9080 timing diagrams ? plx technology, inc., 1997 page 180 version 1.02 a does not change, unaligned has own cycle with ads# d0 d1 d9 d2 d3 d4 d6 d7 d8 lad[3:2] d5 a+40 d10 owned by local bus or another bus master dma continues where it left off give up local bus when programmable breq is asserted 0ns 250ns 500ns lclk lhold lholda ads# ale blast# lbe[3:0]# lw/r# lad[31:0] labs[3:2] dt/r# den# bterm# readyi# breq dma burst suspended by breq. no wait states, burst enabled, bterm enabled, 32 bit local bus. timing diagram 8-78. (j mode) pci 9080 write to local bus breq asserted
section 8 pci 9080 timing diagrams ? plx technology, inc., 1997 page 181 version 1.02 8.5 s mode a a + 8 [15:0] [31:16] [15:0] [31:16] [15:0] [31:16] [15:0] [31:16] a a+4 a+12 a a+2 a+4 a+6 a+8 a+10 a+12 a+14 a 0ns 100ns 200ns 300ns 400ns 5 lclk lclk lhold lholda as# blast# la[31:16] lbe[1:0]# labs[3:1] lad[16:1] bterm# readyi# no wait states, bterm enabled. timing diagram 8-79. (s mode) pci 9080 dma or direct slave two lword burst write to 16 bit local bus
section 8 pci 9080 timing diagrams ? plx technology, inc., 1997 page 182 version 1.02 addr dp0 dp1 data 0 data 1 cs or la[31:29] match s[2:0] abcd addr start word addr next word addr note: clock is twice frequency 0ns 50ns 100ns 150ns 200ns 250n s local bus lclk la[31:16] lad[15:1] labs1 cs# ads# lbe[1:0]# lw/r# blast# dp[3:0] readyo# timing diagram 8-80. (s mode) local bus read from pci 9080 cfg registers
section 8 pci 9080 timing diagrams ? plx technology, inc., 1997 page 183 version 1.02 addr pchk0 pchk1 data 0 data 1 byte enables for data word 0 byte enables for data word 1 cs or la[31:29] match s[2:0] a addr note: clock is 2x, time scale is for 66 mhz, max local bus = 32 addr start word addr next word addr bc d 0ns 50ns 100ns 150ns 200ns 250ns local bus clk la[31:16] lad[15,1] labs[3:2] labs1 cs# as# lbe[1:0]# lw/r# blast# readyo# pchk# timing diagram 8-81. (s mode) local bus write to pci 9080 cfg registers


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